Table of Contents
Advertisement
11.3.3.6
ATA Drive Sector Count Register—MBAR + 0x3A68
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:7
Data
8:31
—
11.3.3.7
ATA Drive Sector Number Register—MBAR + 0x3A6C
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:7
Data
8:31
—
Freescale Semiconductor
Table 11-24. ATA Drive Sector Count Register
2
3
4
5
6
Data
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Bit content is command dependent. For most read/write commands, this register indicates
the total number of sectors requested for transfer.
Register is written only when ATA drive status register bits BSY and DRQ equal 0 and
DMACK is not asserted. If register is written when BSY and DRQ bits are set to 1, the result
is indeterminate.
Register content is not valid when drive is in sleep mode.
Reserved
Table 11-25. ATA Drive Sector Number Register
2
3
4
5
6
Data
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Bit content is command dependent. For most commands, this register indicates the data
transfer starting sector number for when CHS addressing is enabled. This register indicates
part of the LBA address when the LBA addressing is enabled.
Register is written only when ATA drive status register bits BSY and DRQ equal 0 and
DMACK is not asserted. If register is written when BSY and DRQ bits are set to 1, the result
is indeterminate.
Register content is not valid when drive is in sleep mode.
Reserved
MPC5200B Users Guide, Rev. 1
7
8
9
10
11
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
7
8
9
10
11
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
ATA Register Interface
12
13
14
15
Reserved
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
Reserved
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
11-15
Advertisement
Table of Contents
