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16
17
R
W
RESET:
X
X
Note: X: Bit is not reset and must be initialized.
Bits
Name
0:31
IADDR2
14.5.18
FEC Descriptor Group Address 1 Register—MBAR + 0x3120
The GADDR1 register is written by the user. This register contains the upper 32bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. This register must be initialized.
msb 0
1
R
W
RESET:
X
X
16
17
R
W
RESET:
X
X
Note: X: Bit is not reset and must be initialized.
Bits
Name
0:31
GADDR1
14.5.19
FEC Descriptor Group Address 2 Register—MBAR + 0x3124
The GADDR2 register is written by the user. The GADDR2 register contains the lower 32bits of the 64-bit hash table used in the address
recognition process for receive frames with a multicast address. This register must be initialized.
msb 0
1
R
W
RESET:
X
X
Freescale Semiconductor
18
19
20
21
22
X
X
X
X
X
The lower 32bits of the 64-bit hash table used in the address recognition process for receive
frames with a unicast address.
• Bit 31 contains hash index bit 31.
• Bit 0 contains hash index bit 0.
Table 14-27. FEC Descriptor Group Address 1 Register
2
3
4
5
6
X
X
X
X
X
18
19
20
21
22
X
X
X
X
X
The GADDR1 register contains the upper 32bits of the 64-bit hash table used in the address
recognition process for receive frames with a multicast address.
• Bit 31 contains hash index bit 63.
• Bit 0 contains hash index bit 32.
Table 14-28. FEC Descriptor Group Address 2 Register
2
3
4
5
6
X
X
X
X
X
MPC5200B Users Guide, Rev. 1
23
24
25
26
27
IADDR2
X
X
X
X
Description
7
8
9
10
11
GADDR1
X
X
X
X
23
24
25
26
27
GADDR1
X
X
X
X
Description
7
8
9
10
11
GADDR2
X
X
X
X
FEC Registers—MBAR + 0x3000
28
29
30
31 lsb
X
X
X
X
X
12
13
14
15
X
X
X
X
X
28
29
30
31 lsb
X
X
X
X
X
12
13
14
15
X
X
X
X
X
14-25
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