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13.15.8
SDMA Task Control 0 Register—MBAR + 0x121C
SDMA Task Control 1 Register—MBAR + 0x121E
msb 0
1
R
En
Val
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0
EN
1
Val
2
Alw Init
3:7
IN[4:0]
8
Auto Start
Freescale Semiconductor
Table 13-8. SDMA Task Control 0 Register
SDMA Task Control 1 Register
2
3
4
5
6
Alw
IN[4:0]
Init
0
0
0
0
0
18
19
20
21
22
TCR1 (same as for TCR0)
0
0
0
0
0
Each of the sixteen tasks has an associated task control register. Only one register is
shown. At system reset, all bits are initialized to logic zeros.
Enable - Task Enable
0 = Disabled
1 = Enabled
This bit can be set or cleared by the programmer at any time when a task is enabled or
disabled. This bit is also set by the PTD logic if the auto-restart bit is set and the task
completes.
Valid - Initiator Number is Valid
0 = Initiator is not valid
1 = Initiator is valid
This bit is set by the engine logic when it obtains the requestor value from the first DRD
that is parsed. This bit is cleared by the logic when the task completes. At system reset,
this bit is cleared.
Always Init - Decode of the always initiator
0 = The always initiator is not being used
1 = The always initiator is being used
This bit is a status bit only and is set and cleared by writing the initiator number into the
Task Control Register.
InitNum[4:0] - Initiator number from task descriptor
These bits are registered when the SDMA engine has parsed the first DRD to obtain the
requestor number. These bits are cleared by system reset. These bits can be written by the
programmer when the Hold Init Num bit is set or being set and the task is not enabled.
At system reset, these bits are cleared.
Auto-Start - Task Start
0 = Task will not restart within program control
1 = Task will restart at end of task automatically.
This bit can be set or cleared by the programmer at any time. This bit is also cleared if the
SDMA engine encounters an error in the task. At system reset, this bit is cleared.
MPC5200B Users Guide, Rev. 1
BestComm DMA Registers—MBAR+0x1200
7
8
9
10
11
Auto
High
Hold
Rsvd
Start
En
0
0
0
0
23
24
25
26
27
0
0
0
0
Description
12
13
14
15
AS [3:0]
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
13-9
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