Freescale Semiconductor MPC5200B User Manual page 301

Registers
10.3 Registers
MPC5200B has several sets of registers that control and report status for the different interfaces to the PCI controller: PCI Type 0
Configuration Space Registers, General Status/Control Registers, and Communication Sub-System Interface Registers. All of these registers
are accessible as offsets of MBAR (the PCI interface is located starting at offset 0x0D00 relative to the MBAR register's value, while the
BestComm interface starts at offset 0x3800). As an XL bus master, an external PCI bus master can access MBAR space for register updates
and the internal SRAM.
PCI_RST is controlled by a bit in the register space and must first be cleared before external PCI
devices wake-up. In other words, an external PCI master cannot load configuration software across
the PCI bus until this bit is cleared by internal means.
All registers are accessible at an offset of MBAR in the memory space. There are two module offsets for PCI configuration space. One is
allocated to the Communication Sub-System Interface registers and the other to all other PCI Controller Registers including the standard Type
0 PCI Configuration Space. Software reads from unimplemented registers return 0x00000000 and writes have no effect. See
Internal Register Memory Map
Register
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
...
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
...
0x5C
0x60
0x64
0x68
0x6C
0x70
10-4
for module offsets and descriptions of module responses.
Table 10-2. PCI Register Map
Mnemonic
PCI Type 0 Configuration Registers
PCIIDR
PCISCR
PCICCRIR
PCICR1
PCIBAR0
PCIBAR1
PCICCPR
PCISID
PCIERBAR
PCICPR
PCICR2
General Control/Status Registers
PCIGSCR
PCITBATR0
PCITBATR1
PCITCR
PCIIW0BTAR
MPC5200B Users Guide, Rev. 1
NOTE
Name
Device ID/Vendor ID
Status/Command
Class Code/Revision ID
Configuration 1Register
Base Address Register 0
Base Address Register 1
Reserved
Cardbus CIS Pointer
Subsystem ID/Subsystem Vendor ID
Expansion ROM
Capabilities Pointer
Reserved
Configuration 2 Register
Reserved
Global Status/Control Register
Target Base Address Translation Register 0
Target Base Address Translation Register 1
Target Control Register
Initiator Window 0 Base/Translation Address Register
Section 3.2,
Freescale Semiconductor