Configuration Register 1—Mbar + 0X0108 - Freescale Semiconductor MPC5200B User Manual

Device Structure
64Mbit 8Mx8bit
128Mbit 8Mx16bit
16Mx8bit
256Mbit 8Mx32bit
16Mx16bit
32Mx8bit
512Mbit 16Mx32bit
32Mx16bit
64Mx8bit
1Gbit 32Mx32bit
64Mx16bit
2Gbit 64Mx32bit
a
All MEM_MA pins are driven in all cases, but only the bits used by memory are listed.
8.7.3 Configuration Register 1—MBAR + 0x0108
The 32-bit read/write Configuration register 1 stores delay values necessary between specific SDRAM commands. During initialization,
software loads values to the register according to the SDRAM information obtained from the data sheet. This register is reset only by a
power-up reset signal.
The Read and Write Latency fields govern the relative timing of commands and data, and must be exact values. All other fields govern the
relative timing from one command to another, they have minimum values but any larger value is also legal (but with decreased performance).
The "suggested values" are based on the maximum routing delay of memory signals and the MPC5200B maximum memory frequency of
133MHz; they do not guarantee maximum performance for actual board routing delay or operating frequency.
The minimum values of certain fields can be different for SDR and DDR SDRAM, even if the data sheet timing is the same, because:
• In SDR mode, the Memory Controller counts the delay in MEM_CLK
• In DDR mode, the Memory Controller counts the delay in 2xMEM_CLK (also referred to as MEM_CLK2)
MEM_CLK—Memory Controller clock—is the speed of the SDRAM interface and is equal to the internal XL bus clock.
MEM_CLK is fixed at boot time along with the XL bus clock, via the HW RESET WORD setting. It is an integer multiple of the
external reference clock (e.g., 66MHz, 99MHz or 132MHz if a 33MHz reference is used).
Freescale Semiconductor
Table 8-9. 16-Bit SDRAM Address Multiplexing
Row bits ×
Col bits ×
hi_
Bank bits addr 4
a
12x9x2 0 —
12x9x2 0 —
12x10x2 0 —
13x9x2 1 —
12x9x2 0 —
12x10x2 0 —
13x9x2 1 —
12x11x2 0 —
13x10x2 1 —
12x10x2 0 —
13x9x2 1 —
12x11x2 0 —
13x10x2 1 —
12x12x2 0 — CA12 CA11
13x11x2 1 — CA11
12x11x2 0 —
13x10x2 1 —
12x12x2 0 — CA12 CA11
13x11x2 1 — CA11
12x12x2 0 — CA12 CA11
13x11x2 1 — CA11
MPC5200B Users Guide, Rev. 1
Memory Controller Registers (MBAR+0x0100:0x010C)
Internal XLA[4:30]
5 6 7 8
— — — RA[11:0]
— — — RA[11:0]
— — CA9
— — RA12
— — — RA[11:0]
— — CA9
— — RA12
— CA11 CA9
— CA9 RA12
— — CA9 RA[11:0]
— — RA12
— CA11 CA9
— CA9 RA12
CA9
CA9 RA12
— CA11 CA9 RA[11:0]
— CA9 RA12
CA9
CA9 RA12
CA9 RA[11:0]
CA9 RA12
9:19 20:21 22:30
BA CA
[1:0] [8:0]
BA CA
[1:0] [8:0]
BA CA
[1:0] [8:0]
BA CA
[1:0] [8:0]
BA CA
[1:0] [8:0]
BA CA
[1:0] [8:0]
8-25