Freescale Semiconductor MPC5200B User Manual page 311

Registers
16 17
R Rsvd BME
W
RESET 0 0
Bits Name
0 Reserved
1 Broken Master
Detected
(BM)
2 PERR
Detected
(PE)
3 SERR
Detected
(SE)
4 Reserved
5:7 XL Bus_clk to
PCI_CLK
differential
(read only)
8:12 Reserved
13:15 ipg_clk to
PCI_CLK
differential
(read only)
16 Reserved
17 Broken Master
Interrupt Enable
(BME)
18 Parity Error
Interrupt Enable
(PEE)
19 System Error
Interrupt Enable
(SEE)
10-14
18 19 20 21 22
PEE SEE
0 0 0 0
Unused bit. Software should write zero to this register.
This bit is set when the PCI Arbiter detects a broken external PCI master.
Note: In case of broken master detection the external PCI request will be ignored until
external deassertion of PCI request or until a software reset (PCI Arbiter Softreset) or by
Hardreset is detected. After broken master detection (PCI bus idle for 16 clocks) the
arbiter will ignore any FRAME# assertion.
A CPU interrupt will be generated if the PCIGSCR[BME] bit is set. This is a RWC
(Read/WriteClear) bit: to clear it, software must write a '1' at this position.
This bit is set when the PCI Parity Error line, PERR, asserts (any device). A CPU interrupt
will be generated if the PCIGSCR[PEE] bit is set. This is a RWC (Read/WriteClear) bit: to
clear it, software must write a '1' at this position.
This bit is set when a PCI System Error line, SERR, asserts (any device). A CPU interrupt
will be generated if the PCIGSCR[SEE] bit is set. This is a RWC (Read/WriteClear) bit: to
clear it, software must write a '1' at this position.
Unused bit. Software should write zero to this register.
This bit field stores the XL bus clock to the PCI clock divide ratio. This field is read-only
and the reset value is determined by the PLL multiplier (either 1, 2, or 4). Software can
read these bits to determine a valid ratio. If the register contains a differential value that
does not reflect the PLL settings, the PCI controller could malfunction.
Unused bits. Software should write zero to this register.
This bit field stores the Slave bus clock to the PCI clock divide ratio. This field is read-only
and the reset value is determined by the PLL multiplier (either 1, 2, or 4). Software can
read these bits to determine a valid ratio. If the register contains a differential value that
does not reflect the PLL settings, the PCI controller could malfunction.
Unused bit. Software should write zero to this register.
This bit enables CPU Interrupt generation when a broken Master is detected. When
enabled, software must clear the BM status bit to clear the interrupt condition.
This bit enables CPU Interrupt generation when the PCI Parity Error signal, PERR, is
sampled asserted. When enabled and PERR asserts, software must clear the PE status
bit to clear the interrupt condition.
This bit enables CPU Interrupt generation when a PCI System Error is detected on the
SERR line. When enabled and SERR asserts, software must clear the SE status bit to
clear the interrupt condition.
MPC5200B Users Guide, Rev. 1
23 24 25 26
Reserved
0 0 0 0 0
Description
27 28 29 30 31 lsb
PR
0 0 0 0 1
Freescale Semiconductor