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System Level Optimization
3.3.2.1
Cache Configuration
The Intel XScale® Microarchitecture allows users to define memory regions whose cache policies
can be set by the user. To support these various memory regions, OS configures the page-tables
accordingly.
The performance of application code depends on what cache policy used for data objects. A
description of when to use a particular policy is described below.
If the application is running under an OS, then the OS may restrict the application from using
certain cache policies.
3.3.2.1.1
Cache Configuration: Write-through and Write-back Cached Memory Regions
Write-back mode avoids some memory transactions by allowing data to collect in the data cache
before eventually being written to memory when the cache line is evicted. When cache lines are
evicted, the writes coalesce and are efficiently written to memory. This differs from write-through
mode where writes are always written to memory immediately. Write-through memory regions
generate more data traffic on the bus and consume more power due to increased bus activity. The
write-back policy is recommended to be used whenever possible. However, in a multi bus master
environment it may be necessary to use a write-through policy if data is shared across multiple
masters. In such a situation all shared memory regions should use write-through policy. Memory
regions that are private to a particular master should use the write-back policy.
3.3.2.1.2
Cache Configuration: Read Allocate and Read-write Allocate Memory Regions
Write-back with read/write allocate caches cause an additional read from the memory during a
write miss. Subsequent read and write performance may be improved by more frequent cache hits.
Most of the regular data and the stack for applications should be allocated to a read-write allocate
region. Data that is write only (or data that is written to and subsequently not used for a long time)
should be placed in a read allocate region. Under the read allocate policy, if a cache write miss
occurs, a new cache line is not allocated, and hence does not evict data from the data cache.
Memory intensive operations like a memcopy can actually be slowed down by the extra reads
required for the write allocate policy.
3.3.2.1.3
Cache Configuration: Noncacheable Regions
Noncachable memory regions (X=0, C=0, B=0) are frequently needed for I/O devices. For these
devices the relevant device registers and memory spaces are mapped as noncacheable. In some
cases making the noncacheable regions bufferable (X=0, C=0, and B =1) can accelerate the
memory performance due to write coalescing. There are cases where a noncached memory regions
must be set as nonbufferable (B=0):
•
Any device where consecutive writes to the same address could be over-written in the write
buffer before reaching the target device (e.g. FIFOs).
•
Devices where read/write order to the device is required. When coalescing occurs, writes
occur in numerical address order, not in the temporal order.
3.3.2.2
Creating Scratch RAM in the Internal SRAM
A very simple method for creating a fast scratch RAM is to allocate a portion of the Internal SRAM
for this purpose. This will allow data mapped to this area to be accessed much more quickly than if
it resided in external memory. Additionally, there are no considerations for cache locking, as are
discussed in the next section,
3-6
Section 3.3.2.3, "Creating Scratch RAM in Data
Intel® PXA27x Processor Family Optimization Guide
Cache".
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