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Data Cache
6.2
Data Cache and Mini-Data Cache Operation
The following refers to the data cache and mini-data cache as one cache (data/mini-data) since their
behavior is the same when accessed.
6.2.1
Operation When Caching is Enabled
When the data/mini-data cache is enabled for an access, the data/mini-data cache compares the
address of the request against the addresses of data that it is currently holding. If the line containing
the address of the request is resident in the cache, the access hits the cache. For a load operation the
cache returns the requested data to the destination register and for a store operation the data is
stored into the cache. The data associated with the store may also be written to external memory if
write-through caching is specified for that area of memory. If the cache does not contain the
requested data, the access misses the cache, and the sequence of events that follows depends on the
configuration of the cache, the configuration of the MMU and the page attributes. These are
described in
6.2.2
Operation When Data Caching is Disabled
The data/mini-data cache is still accessed even when it is disabled. If a load hits the cache it will
return the requested data to the destination register. If a store hits the cache, the data is written into
the cache.
Any access that misses the cache will not allocate a line in the cache when it's disabled, even if the
MMU is enabled and the memory region's cacheability attribute is set. Any data reads or writes
that miss in the cache will be directed to memory as controlled by the MMU. If both the data cache
and MMU are disabled then cache misses will be issued as cycles on the application processor
internal memory bus.
Disabling the cache prevents cache line refilling, but not the cache lookup from the processor.
6.2.3
Cache Policies
6.2.3.1
Cacheability
Data at a specified address is cacheable given the following:
•
the MMU is enabled
•
the cacheable attribute is set in the descriptor for the accessed address
•
and the data/mini-data cache is enabled
6.2.3.2
Read Miss Policy
The following sequence of events occurs when a cacheable (see
load operation misses the data cache:
1. The fill buffer is checked to see if an outstanding fill request already exists for that line.
If so, the current request is placed in the pending buffer and waits until the previously
requested fill completes, after which it accesses the cache again, to obtain the request data and
returns it to the destination register.
6-4
Section 6.2.3.2, "Read Miss Policy"
and
Section 6.2.3.3, "Write Miss
Section 6.2.3.1,
Intel® XScale™ Microarchitecture User's Manual
Policy".
"Cacheability")
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