Page Table Configuration; Page Attributes For Instructions; Page Attributes For Data Access; Data Cache And Buffer Behavior When X = 1 - Intel PXA270 Optimization Manual

With B=0 and CCCR[A] = 1" table
With B=1 and CCCR[A] = 1"
instead.
3.2.3

Page Table Configuration

Three bits for each page are used to configure each memory page's cache behavior. Different
values of X,C,B determine the caching, reading and writing, and buffering policies of the pages.
3.2.3.1

Page Attributes For Instructions

When examining these bits in a descriptor, the instruction cache only utilizes the C bit. If the C bit
is clear, the instruction cache considers a code fetch from that memory to be noncacheable, and will
not fill a cache entry. If the C bit is set, then fetches from the associated memory region is cached.
3.2.3.2

Page Attributes For Data Access

For data access, all three attributes are important. If the X bit for a descriptor is zero, the C and B
bits operate as defined by the ARM* architecture. This behavior is detailed in
If the X bit for a descriptor is one, the C and B bits behave differently, as shown in
load and store buffer behavior in Intel XScale® Microarchitecture is explained in
"Write Buffer Behavior"
Table 3-3. Data Cache and Buffer Behavior when X = 0
C B Cacheable?
0 0
0 1
1 0
1 1
† Normally, the processor continues executing after a data access if no dependency on that access is
encountered. With this setting, the processor stalls execution until the data access completes. This
guarantees to software that the data access has taken effect by the time execution of the data access
instruction completes. External data aborts from such accesses are imprecise.
Table 3-4. Data Cache and Buffer Behavior when X = 1 (Sheet 1 of 2)
C B Cacheable?
0 0
0 1
Intel® PXA27x Processor Family Optimization Guide
and the
table in the Intel® PXA27x Processor Family Developer's Manual
and Section 2.2.4.1.2, "Read Buffer Behavior"
Load Buffering
and Write
Coalescing?
N N
N Y
Y Y
Y Y
Load Buffering
and Write
Coalescing?
— —
N Y
System Level Optimization
"Core PLL Output Frequencies for 13 MHz Crystal
Line Allocation
Write Policy
Policy
— —
— —
Write-through Read Allocate
Write-back Read Allocate
Line Allocation
Write Policy
Policy
— —
— —
Table 3-3.
Table 3-4. The
Section 2.2.4.1.1,
Notes
†
Stall until complete
Notes
Unpredictable -- do not use
Writes will not coalesce into
†
buffers
3-3