Intel BX80605X3430 - Xeon 2.4 GHz Processor Manuals

Manuals and User Guides for Intel BX80605X3430 - Xeon 2.4 GHz Processor. We have 1 Intel BX80605X3430 - Xeon 2.4 GHz Processor manual available for free PDF download: Datasheet

Intel BX80605X3430 - Xeon 2.4 GHz Processor Datasheet

Intel BX80605X3430 - Xeon 2.4 GHz Processor Datasheet (98 pages)

Data Sheet

Brand: Intel | Category: Computer Hardware | Size: 0 MB

Table of Contents

Table of Contents
3
Revision History
7
1 Introduction

9
- Intel Xeon Processor 3400 Series Platform Diagram
  10
- Processor Feature Details
  11
  - Supported Technologies
    11
- Interfaces
  11
  - System Memory Support
    11
- Intel ® Xeon ® Processor 3400 Series Supported Memory Summary
  11
- Power Management Support
  14
  - Processor Core
    14
  - System
    14
  - Memory Controller
    14
  - PCI Express
    14
- Thermal Management Support
  15
- Package
  15
- Terminology
  15
- Related Documents
  17
2 Interfaces

19
3 Technologies

31
4 Power Management

35
- ACPI States Supported
  35
- Processor Core/Package State Support
  35
  - PCI Express* Link States
    36
  - Interface State Combinations
    36
- Processor Core Power Management
  36
- G, S, and C State Combinations
  36
  - Enhanced Intel ® Speedstep ® Technology
    37
  - Low-Power Idle States
    37
- Idle Power Management Breakdown of the Processor Cores
  37
- Thread and Core C-State Entry and Exit
  38
- Coordination of Thread Power States at the Core Level
  38
  - Requesting Low-Power Idle States
    39
  - Core C-States
    39
- P_Lvlx to MWAIT Conversion
  39
  - Core C0 State
    40
  - Core C1/C1E State
    40
  - Core C3 State
    40
  - Core C6 State
    40
  - C-State Auto-Demotion
    40
  - Package C-States
    41
- Coordination of Core Power States at the Package Level
  41
  - Package C0
    42
  - Package C1/C1E
    42
- Package C-State Entry and Exit
  42
  - Package C3 State
    43
  - Package C6 State
    43
- IMC Power Management
  43
  - Disabling Unused System Memory Outputs
    43
  - DRAM Power Management and Initialization
    44
    
    Initialization Role of CKE
    44
    
    Conditional Self-Refresh
    44
    
    Dynamic Power down Operation
    44
- Targeted Memory State Conditions
  44
  - DRAM I/O Power Management
    45
- PCI Express* Power Management
  45
5 Thermal Management

47
6 Signal Description

49
- Signal Description Buffer Types
  49
- System Memory Interface
  50
- Memory Channel a
  50
- Memory Channel B
  51
- Memory Reference and Compensation
  52
- Reset and Miscellaneous Signals
  52
- PCI Express* Based Interface Signals
  53
- DMI-Processor to PCH Serial Interface
  53
- PLL Signals
  54
- Intel ® Flexible Display Interface Signals
  54
- Intel ® Flexible Display Interface
  54
  - JTAG/ITP Signals
    55
- Jtag/Itp
  55
- Graphics and Memory Power Signals
  59
  - Ground and NCTF
    60
  - Processor Internal Pull Up/Pull down
    60
7 Electrical Specifications

61
8 Processor Land and Signal Information

79

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