ST STM32G0 1 Series Reference Manual page 1127

RM0444
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 TXFT: TXFIFO threshold flag
Bit 26 RXFT: RXFIFO threshold flag
Bit 25 Reserved, must be kept at reset value.
Bit 24 RXFF: RXFIFO full
Bit 23 TXFE: TXFIFO empty
Bit 22 REACK: Receive enable acknowledge flag
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
Bit 21 TEACK: Transmit enable acknowledge flag
Bit 20 WUF: Wakeup from low-power mode flag
Note: When UESM is cleared, WUF flag is also cleared.
Low-power universal asynchronous receiver transmitter (LPUART)
This bit is set by hardware when the TXFIFO reaches the threshold programmed in
TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations.
An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the LPUART_CR3 register.
0: TXFIFO does not reach the programmed threshold.
1: TXFIFO reached the programmed threshold.
This bit is set by hardware when the RXFIFO reaches the threshold programmed in
RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An
interrupt is generated if the RXFTIE bit = 1 (bit 27) in the LPUART_CR3 register.
0: Receive FIFO does not reach the programmed threshold.
1: Receive FIFO reached the programmed threshold.
This bit is set by hardware when the number of received data corresponds to
RXFIFO size + 1 (RXFIFO full + 1 data in the LPUART_RDR register.
An interrupt is generated if the RXFFIE bit = 1 in the LPUART_CR1 register.
0: RXFIFO is not full
1: RXFIFO is full
This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one
data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4)
in the LPUART_RQR register.
An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the LPUART_CR1 register.
0: TXFIFO is not empty
1: TXFIFO is empty
This bit is set/reset by hardware, when the Receive Enable value is taken into account by
the LPUART.
It can be used to verify that the LPUART is ready for reception before entering low-power
mode.
kept at reset value.
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the LPUART.
It can be used when an idle frame request is generated by writing TE = 0, followed by
TE = 1 in the LPUART_CR1 register, in order to respect the TE = 0 minimum period.
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register.
An interrupt is generated if WUFIE = 1 in the LPUART_CR3 register.
If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value
RM0444 Rev 5 1127/1390
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