ST STM32G0 1 Series Reference Manual page 1130

Low-power universal asynchronous receiver transmitter (LPUART)
Bit 3 ORE: Overrun error
Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register
Bit 2 NE: Start bit noise detection flag
Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit
Bit 1 FE: Framing error
Note: This error is associated with the character in the LPUART_RDR.
Bit 0 PE: Parity error
Note: This error is associated with the character in the LPUART_RDR.
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This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a
software, writing 1 to the ORECF, in the LPUART_ICR register.
An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the LPUART_CR1 register.
0: No overrun error
1: Overrun error is detected
is overwritten. An interrupt is generated if the ORE flag is set during multi buffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in
the LPUART_CR3 register.
This bit is set by hardware when noise is detected on the start bit of a received frame. It is
cleared by software, writing 1 to the NECF bit in the LPUART_ICR register.
0: No noise is detected
1: Noise is detected
which itself generates an interrupt. An interrupt is generated when the NE flag is set
during multi buffer communication if the EIE bit is set.
This error is associated with the character in the LPUART_RDR.
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register.
When transmitting data in Smartcard mode, this bit is set when the maximum number of
transmit attempts is reached without success (the card NACKs the data frame).
An interrupt is generated if EIE = 1 in the LPUART_CR1 register.
0: No Framing error is detected
1: Framing error or break character is detected
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the LPUART_ICR register.
An interrupt is generated if PEIE = 1 in the LPUART_CR1 register.
0: No parity error
1: Parity error
RM0444 Rev 5
RM0444