STMicroelectronics STM32WL5 Series Reference Manual page 1105

RM0453
one is completed. The latency of the second write access can be up to 2x PCLK1 +
6 x I2CCLK.
31 30 29
Res. Res. Res. Res.
15 14 13
OA2EN Res. Res. Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 OA2EN: Own address 2 enable
Bits 14:11 Reserved, must be kept at reset value.
Bits 10:8 OA2MSK[2:0]: Own address 2 masks
Note: These bits can be written only when OA2EN = 0.
Bits 7:1 OA2[7:1]: Interface address
Note: These bits can be written only when OA2EN = 0.
Bit 0 Reserved, must be kept at reset value.
34.7.5 I2C timing register (I2C_TIMINGR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: No wait states
31 30 29 28
PRESC[3:0]
rw rw rw rw
15 14 13 12
SCLH[7:0]
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. OA2MSK[2:0]
rw rw
0: Own address 2 disabled. The received slave address OA2 is NACKed.
1: Own address 2 enabled. The received slave address OA2 is ACKed.
000: No mask
001: OA2[1] is masked and don't care. Only OA2[7:2] are compared.
010: OA2[2:1] are masked and don't care. Only OA2[7:3] are compared.
011: OA2[3:1] are masked and don't care. Only OA2[7:4] are compared.
100: OA2[4:1] are masked and don't care. Only OA2[7:5] are compared.
101: OA2[5:1] are masked and don't care. Only OA2[7:6] are compared.
110: OA2[6:1] are masked and don't care. Only OA2[7] is compared.
111: OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved)
7-bit received addresses are acknowledged.
As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and
0b1111xxx) are not acknowledged even if the comparison matches.
7-bit addressing mode: 7-bit address
27 26 25
Res. Res. Res.
11 10 9
rw rw rw
Inter-integrated circuit (I2C) interface
24 23 22
Res. Res. Res.
8 7 6
rw rw rw
24 23 22
Res. SCLDEL[3:0]
rw rw
8 7 6
rw rw rw
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OA2[7:1]
rw rw rw rw
21 20 19 18
SDADEL[3:0]
rw rw rw rw
5 4 3 2
SCLL[7:0]
rw rw rw rw
17 16
Res. Res.
1 0
Res.
rw
17 16
rw rw
1 0
rw rw
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