STMicroelectronics STM32WL5 Series Reference Manual page 1027

RM0453
32.6.19 RTC masked interrupt status register (RTC_MISR)
Address offset: 0x54
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 SSRUMF: SSR underflow masked flag
Bit 5 ITSMF: Internal timestamp masked flag
Bit 4 TSOVMF: Timestamp overflow masked flag
Bit 3 TSMF: Timestamp masked flag
Bit 2 WUTMF: Wake-up timer masked flag
Bit 1 ALRBMF: Alarm B masked flag
This flag is set by hardware when the alarm B interrupt occurs.
Bit 0 ALRAMF: Alarm A masked flag
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This flag is set by hardware when the SSR underflow interrupt occurs.
This flag is set by hardware when a timestamp on the internal event occurs and
timestampinterrupt is raised.
This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,
an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit
is cleared.
This flag is set by hardware when a timestamp interrupt occurs.
If ITSF flag is set, TSF must be cleared together with ITSF.
This flag is set by hardware when the wake-up timer interrupt occurs.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
This flag is set by hardware when the alarm A interrupt occurs.
24 23 22
Res. Res. Res.
8 7 6
SSR
Res. Res.
UMF
r
RM0453 Rev 5
Real-time clock (RTC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
ITS TSOV TS WUT
MF MF MF MF
r r r r
17 16
Res. Res.
1 0
ALRB ALRA
MF MF
r r
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