STMicroelectronics STM32WL5 Series Reference Manual page 1096

Inter-integrated circuit (I2C) interface
34.4.17 DMA requests
Transmission using DMA
DMA (direct memory access) can be enabled for transmission by setting the TXDMAEN bit
in the I2C_CR1 register. Data is loaded from an SRAM area configured using the DMA
peripheral (see
register whenever the TXIS bit is set.
Only the data are transferred with DMA.
•
In master mode: the initialization, the slave address, direction, number of bytes and
START bit are programmed by software (the transmitted slave address cannot be
transferred with DMA). When all data are transferred using DMA, the DMA must be
initialized before setting the START bit. The end of transfer is managed with the
NBYTES counter. Refer to
•
In slave mode:
–
–
•
For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.
Refer to
Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.
Reception using DMA
DMA (direct memory access) can be enabled for reception by setting the RXDMAEN bit in
the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area
configured using the DMA peripheral (refer to ) whenever the RXNE bit is set. Only the data
(including PEC) are transferred with DMA.
•
In master mode, the initialization, the slave address, direction, number of bytes and
START bit are programmed by software. When all data are transferred using DMA, the
DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter.
•
In slave mode with NOSTRETCH = 0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
•
If SMBus is supported (see
NBYTES counter. Refer to
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.
34.4.18 Debug mode
When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_ configuration bits in the
DBG module.
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Section 13: Direct memory access controller
With NOSTRETCH = 0, when all data are transferred using DMA, the DMA must
be initialized before the address match event, or in ADDR interrupt subroutine,
before clearing ADDR.
With NOSTRETCH = 1, the DMA must be initialized before the address match
event.
SMBus slave transmitter
Master transmitter.
and SMBus master
Section 34.3): the PEC transfer is managed with the
SMBus Slave receiver
RM0453 Rev 5
(DMA)) to the I2C_TXDR
transmitter.
and SMBus master receiver.
RM0453