STMicroelectronics STM32WL5 Series Reference Manual page 1047

RM0453
33.6.9 TAMP monotonic counter register (TAMP_COUNTR)
Address offset: 0x040
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
r r r
15 14 13
r r r
Bits 31:0 COUNT[31:0]:
33.6.10 TAMP backup x register (TAMP_BKPxR)
Address offset: 0x100 + 0x04 * x, (x = 0 to 19)
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 BKP[31:0]:
28 27 26 25
r r r r
12 11 10 9
r r r r
This register is read-only only and is incremented by one when a write access is done to this
register. This register cannot roll-over and is frozen when reaching the maximum value.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
The application can write or read data to and from these registers.
They are powered-on by V
reset, and their contents remain valid when the device operates in low-power mode.
In the default configuration this register is reset on a tamper detection event. It is forced to
reset value as long as there is at least one internal or external tamper flag being set. This
register is also reset when the readout protection (RDP) is disabled.
Tamper and backup registers (TAMP)
24 23 22
COUNT[31:16]
r r r
8 7 6
COUNT[15:0]
r r r
24 23 22
BKP[31:16]
rw rw rw
8 7 6
BKP[15:0]
rw rw rw
when V is switched off, so that they are not reset by System
BAT DD
RM0453 Rev 5
21 20 19 18
r r r r
5 4 3 2
r r r r
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw w
17 16
r r
1 0
r r
17 16
rw rw
1 0
rw rw
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