STMicroelectronics STM32WL5 Series Reference Manual page 1049

RM0453
34 Inter-integrated circuit (I2C) interface
34.1 Introduction
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The I C (inter-integrated circuit) bus interface handles communications between the
microcontroller and the serial I
bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm),
Fast-mode (Fm) and Fast-mode Plus (Fm+).
It is also SMBus (system management bus) and PMBus
compatible.
DMA can be used to reduce CPU overload.
34.2 I2C main features
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I C bus specification rev03 compatibility:
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• 1-byte buffer with DMA capability
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Programmable analog and digital noise filters
The following additional features are also available, depending on the product
implementation (see
• SMBus specification rev 3.0 compatibility:
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PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
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Slave and master modes
Multimaster capability
Standard-mode (up to 100 kHz)
Fast-mode (up to 400 kHz)
Fast-mode Plus (up to 1 MHz)
7-bit and 10-bit addressing mode
Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
All 7-bit addresses acknowledge mode
General call
Programmable setup and hold times
Easy to use event management
Optional clock stretching
Software reset
Section 34.3):
Hardware PEC (packet error checking) generation and verification with ACK
control
Command and data acknowledge control
Address resolution protocol (ARP) support
Host and device support
SMBus alert
Timeouts and idle condition detection
Inter-integrated circuit (I2C) interface
C bus. It provides multimaster capability, and controls all I
RM0453 Rev 5
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(power management bus)
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