STMicroelectronics STM32WL5 Series Reference Manual page 1109

RM0453
Bit 8 BERR: Bus error
Note: This bit is cleared by hardware when PE = 0.
Bit 7 TCR: Transfer Complete Reload
Note: This bit is cleared by hardware when PE = 0.
Bit 6 TC: Transfer Complete (master mode)
Note: This bit is cleared by hardware when PE = 0.
Bit 5 STOPF: Stop detection flag
It is cleared by software by setting the STOPCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 4 NACKF: Not Acknowledge received flag
Note: This bit is cleared by hardware when PE = 0.
Bit 3 ADDR: Address matched (slave mode)
Note: This bit is cleared by hardware when PE = 0.
Bit 2 RXNE: Receive data register not empty (receivers)
Note: This bit is cleared by hardware when PE = 0.
Bit 1 TXIS: Transmit interrupt status (transmitters)
Note: This bit is cleared by hardware when PE = 0.
Bit 0 TXE: Transmit data register empty (transmitters)
Note: This bit is set by hardware when PE = 0.
This flag is set by hardware when a misplaced Start or STOP condition is detected whereas
the peripheral is involved in the transfer. The flag is not set during the address phase in slave
mode. It is cleared by software by setting BERRCF bit.
This flag is set by hardware when RELOAD = 1 and NBYTES data have been transferred. It
is cleared by software when NBYTES is written to a non-zero value.
This flag is only for master mode, or for slave mode when the SBC bit is set.
This flag is set by hardware when RELOAD = 0, AUTOEND = 0 and NBYTES data have
been transferred. It is cleared by software when START bit or STOP bit is set.
This flag is set by hardware when a STOP condition is detected on the bus and the
peripheral is involved in this transfer:
– either as a master, provided that the STOP condition is generated by the peripheral.
– or as a slave, provided that the peripheral has been addressed previously during
this transfer.
This flag is set by hardware when a NACK is received after a byte transmission. It is cleared
by software by setting the NACKCF bit.
This bit is set by hardware as soon as the received slave address matched with one of the
enabled slave addresses. It is cleared by software by setting ADDRCF bit.
This bit is set by hardware when the received data is copied into the I2C_RXDR register, and
is ready to be read. It is cleared when I2C_RXDR is read.
This bit is set by hardware when the I2C_TXDR register is empty and the data to be
transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be
sent is written in the I2C_TXDR register.
This bit can be written to '1' by software when NOSTRETCH = 1 only, in order to generate a
TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1).
This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next
data to be sent is written in the I2C_TXDR register.
This bit can be written to '1' by software in order to flush the transmit data register
I2C_TXDR.
Inter-integrated circuit (I2C) interface
RM0453 Rev 5 1109/1450
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