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RM0453
34.7.9
I2C PEC register (I2C_PECR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: No wait states
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PEC[7:0]: Packet error checking register
Note:
If the SMBus feature is not supported, this register is reserved and forced by hardware to
"0x00000000". Refer to
34.7.10
I2C receive data register (I2C_RXDR)
Address offset: 0x24
Reset value: 0x0000 0000
Access: No wait states
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 RXDATA[7:0]: 8-bit receive data
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This field contains the internal PEC when PECEN=1.
The PEC is cleared by hardware when PE = 0.
Section
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Data byte received from the I
Inter-integrated circuit (I2C) interface
24
23
22
Res.
Res.
Res.
8
7
6
Res.
r
r
34.3.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
r
r
2
C bus
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PEC[7:0]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
RXDATA[7:0]
r
r
r
r
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
1111/1450
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