STMicroelectronics STM32WL5 Series Reference Manual page 1106

Inter-integrated circuit (I2C) interface
Bits 31:28 PRESC[3:0]: Timing prescaler
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:20 SCLDEL[3:0]: Data setup time
Note: t
Bits 19:16 SDADEL[3:0]: Data hold time
Note: SDADEL is used to generate t
Bits 15:8 SCLH[7:0]: SCL high period (master mode)
Note: SCLH is also used to generate t
Bits 7:0 SCLL[7:0]: SCL low period (master mode)
Note: SCLL is also used to generate t
Note: This register must be configured when the I2C is disabled (PE = 0).
Note: The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
34.7.6 I2C timeout register (I2C_TIMEOUTR)
Address offset: 0x14
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.
31 30 29
TEXTEN Res. Res.
rw
15 14 13
TIMOUTEN Res. Res.
rw
1106/1450
This field is used to prescale I2CCLK in order to generate the clock period t
data setup and hold counters (refer to
(refer to I2C master initialization).
t = (PRESC + 1) x t
PRESC
This field is used to generate a delay t
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
t .
SCLDEL
t = (SCLDEL + 1) x t
SCLDEL
is used to generate t
SCLDEL
This field is used to generate the delay t
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
t .
SDADEL
t = SDADEL x t
SDADEL PRESC
This field is used to generate the SCL high period in master mode.
t = (SCLH + 1) x t
SCLH PRESC
This field is used to generate the SCL low period in master mode.
t = (SCLL + 1) x t
SCLL PRESC
28 27 26
Res.
rw rw
12 11 10
TIDLE
rw rw rw
I2C timings) and for SCL high and low level counters
I2CCLK
between SDA edge and SCL rising edge. In
SCLDEL
PRESC
timing.
SU:DAT
between SCL falling edge and SDA edge. In
SDADEL
timing.
HD:DAT
and t
SU:STO HD:STA
and t
BUF SU:STA
25 24 23 22
TIMEOUTB[11:0]
rw rw rw rw
9 8 7 6
TIMEOUTA[11:0]
rw rw rw rw
RM0453 Rev 5
PRESC
timing.
timings.
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0453
used for
17 16
rw rw
1 0
rw rw