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Inter-integrated circuit (I2C) interface
34.7.8
I2C interrupt clear register (I2C_ICR)
Address offset: 0x1C
Reset value: 0x0000 0000
Access: No wait states
31
30
29
Res.
Res.
Res.
Res.
15
14
13
ALERT
TIMOU
Res.
Res.
CF
TCF
w
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 ALERTCF: Alert flag clear
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 12 TIMOUTCF: Timeout detection flag clear
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 11 PECCF: PEC Error flag clear
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 10 OVRCF: Overrun/Underrun flag clear
Bit 9 ARLOCF: Arbitration lost flag clear
Bit 8 BERRCF: Bus error flag clear
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 STOPCF: STOP detection flag clear
Bit 4 NACKCF: Not Acknowledge flag clear
Bit 3 ADDRCF: Address matched flag clear
Bits 2:0 Reserved, must be kept at reset value.
1110/1450
28
27
26
25
Res.
Res.
Res.
12
11
10
9
ARLOC
PECCF OVRCF
F
w
w
w
w
Writing 1 to this bit clears the ALERT flag in the I2C_ISR register.
Refer to
Section
34.3.
Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register.
Refer to
Section
34.3.
Writing 1 to this bit clears the PECERR flag in the I2C_ISR register.
Refer to
Section
34.3.
Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
Writing 1 to this bit clears the NACKF flag in I2C_ISR register.
Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also
clears the START bit in the I2C_CR2 register.
24
23
22
Res.
Res.
Res.
8
7
6
BERRC
STOPC
Res.
Res.
F
w
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
NACKC
ADDR
Res.
F
F
CF
w
w
w
RM0453
17
16
Res.
Res.
1
0
Res.
Res.
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