STMicroelectronics STM32WL5 Series Reference Manual page 1107

RM0453
Bit 31 TEXTEN: Extended clock timeout enable
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 TIMEOUTB[11:0]: Bus timeout B
Note: These bits can be written only when TEXTEN = 0.
Bit 15 TIMOUTEN: Clock timeout enable
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 TIDLE: Idle clock timeout detection
Note: This bit can be written only when TIMOUTEN = 0.
Bits 11:0 TIMEOUTA[11:0]: Bus Timeout A
Note: These bits can be written only when TIMOUTEN = 0.
Note:
If the SMBus feature is not supported,
"0x00000000".
34.7.7 I2C interrupt and status register (I2C_ISR)
Address offset: 0x18
Reset value: 0x0000 0001
Access: No wait states
31 30 29
Res. Res. Res. Res.
15 14 13
TIME
BUSY Res. ALERT
OUT
r r
0: Extended clock timeout detection is disabled
1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more
than t is done by the I2C interface, a timeout error is detected (TIMEOUT = 1).
LOW:EXT
This field is used to configure the cumulative clock extension timeout:
In master mode, the master cumulative clock low extend time (t
In slave mode, the slave cumulative clock low extend time (t
t = (TIMEOUTB + TIDLE = 01) x 2048 x t
LOW:EXT
0: SCL timeout detection is disabled
1: SCL timeout detection is enabled: when SCL is low for more than t
high for more than t
IDLE
0: TIMEOUTA is used to detect SCL low timeout
1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
This field is used to configure:
The SCL low timeout condition t
t = (TIMEOUTA + 1) x 2048 x t
TIMEOUT
The bus idle condition (both SCL and SDA high) when TIDLE = 1
t = (TIMEOUTA + 1) x 4 x t
IDLE
Refer to Section
28 27 26 25
Res. Res. Res.
12 11 10 9
PEC
OVR ARLO
ERR
r r r r
(TIDLE = 1), a timeout error is detected (TIMEOUT = 1).
when TIDLE = 0
TIMEOUT
I2CCLK
I2CCLK
this register is reserved and forced by hardware to
34.3.
24 23 22
Res.
r r
8 7 6
BERR TCR TC
r r r
RM0453 Rev 5
Inter-integrated circuit (I2C) interface
LOW:MEXT
) is detected
LOW:SEXT
I2CCLK
TIMEOUT
21 20 19
ADDCODE[6:0]
r r r
5 4 3
STOPF NACKF ADDR RXNE
r r r
) is detected
(TIDLE = 0) or
18 17 16
DIR
r r r
2 1 0
TXIS TXE
r rs rs
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