Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1818

ADSP-SC58x PCIE Register Descriptions
DMA Read Channel 1 and 0 IMWr Data Register
The
PCIE_DMARD_CH01_IMWR_[n]
power on. This register must always have an initialized value because the default is undefined. All fields marked Re-
served must be programmed to 1'b0. This register is not affected by any of the reset signals.
Figure 29-42: PCIE_DMARD_CH01_IMWR_[n] Register Diagram
Table 29-51: PCIE_DMARD_CH01_IMWR_[n] Register Fields
Bit No.
(Access)
15:0 CH0
(R/W)
29–114
register is implemented in RAM whose contents are uninitialized after
15 14 13 12
0 0 0
CH0 (R/W)
Read Channel 0 Data
31 30 29 28
0 0 0
Bit Name
Read Channel 0 Data.
The DMA uses the PCIE_DMARD_CH01_IMWR_[n].CH0 bit field to generate
the data field for the Done or Abort IMWr TLPs it generates for read channel 0.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
27 26 25 24 23 22 21 20
0 0 0 0 0 0 0 0
Description/Enumeration
4 3 2 1 0
0 0 0 0 0
19 18 17 16
0 0 0 0 0