Glossary; Availability Of Peripherals - ST STM32WL55JC Reference Manual

RM0453
This architecture is shown in the figure below.
CPU1
Arm
Cortex-M4 Cortex-M0+
S0 S1 S2
2.1.1 S0: CPU1 I-bus
This bus connects the instruction bus of the CPU1 core to the bus matrix. This bus is used
by the core to fetch instructions. The targets of this bus are the internal Flash memory,
SRAM1and SRAM2.
2.1.2 S1: CPU1 D-bus
This bus connects the data bus of the CPU1 core to the bus matrix. This bus is used by the
core for literal load and debug access. The targets of this bus are the internal Flash memory,
SRAM1 and SRAM2.
2.1.3 S2: CPU1 S-bus
This bus connects the system bus of the CPU1 core to the bus matrix. This bus is used by
the core to access data located in a peripheral or SRAM area. The targets of this bus are the
SRAM1, SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the
AHB2 peripherals and the AHB3 peripherals including the APB3.
2.1.4 S3: CPU2 S-bus
This bus connects the system bus of the CPU2 core to the bus matrix. This bus is used by
the core to fetch instructions, for literal load and debug access, and access data located in a
peripheral or SRAM area. The targets of this bus are the internal Flash memory, SRAM1,
Figure 1. System architecture
CPU2
Arm
DMA1
S3 S4
Bus matrix
DMA2
S5
RM0453 Rev 2
Memory and bus architecture
Flash
memory FLASH
arbiter
SRAM1
SRAM2
AHB1
AHB2
AHB3
when remapped
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