Altera cyclone V Technical Reference page 3060

20-42
ic_intr_mask
ic_intr_mask Fields
Bit
11
m_gen_call
10
m_start_det
9
m_stop_det
8
m_activity
7
m_rx_done
6
m_tx_abrt
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Set only when a General Call address is received and
it is acknowledged. It stays set until it is cleared either
by disabling I2C or when the CPU reads bit 0 of the
ic_clr_gen_call register. I2C stores the received data
in the Rx buffer.
Indicates whether a START or RESTART condition
has occurred on the I2C interface regardless of
whether I2C is operating in slave or master mode.
Indicates whether a STOP condition has occurred on
the I2C interface regardless of whether i2c is
operating in slave or master mode.
This bit captures i2c activity and stays set until it is
cleared. There are four ways to clear it: - Disabling the
i2c - Reading the ic_clr_activity register - Reading the
ic_clr_intr register - System reset Once this bit is set,
it stays set unless one of the four methods is used to
clear it. Even if the I2C module is idle, this bit
remains set until cleared, indicating that there was
activity on the bus.
When the I2C is acting as a slave-transmitter, this bit
is set to 1, if the master does not acknowledge a
transmitted byte. This occurs on the last byte of the
transmission, indicating that the transmission is
done.
This bit indicates if I2C, as an I2C transmitter, is
unable to complete the intended actions on the
contents of the transmit FIFO. This situation can
occur both as an I2C master or an I2C slave, and is
referred to as a 'transmit abort'. When this bit is set to
1, the ic_tx_abrt_source register indicates the reason
why the transmit abort takes places. NOTE: The I2C
flushes/​resets/​empties the TX FIFO whenever this bit
is set. The TX FIFO remains in this flushed state until
the register ic_clr_tx_abrt is read. Once this read is
performed, the TX FIFO is then ready to accept more
data bytes from the APB interface.
Description
cv_5v4
2016.10.28
Access Reset
RW 0x1
RW 0x0
RW 0x0
RW 0x0
RW 0x1
RW 0x1
I2C Controller
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