Watching Control And Status Registers And Pins - Intel IXP2400 User Manual

IXP2400/IXP2800 Network Processors
Developer Workbench
Segments:
Data watch values are broken into 32-bit segments. For example:
A 64-bit value displays as 0xcafecafe 0xcafecafe.
Save:
Data watches are saved with project debug settings.
2.13.12.3

Watching Control and Status Registers and Pins

The Workbench recognizes the control and status register (CSR) and pin names described in the
®
Intel IXP2400 /IXP2800 Network Processor Programmer's Reference Manual. If your project
contains multiple chips, you are prompted to select which chip's register to watch. Similarly, if the
register is Microengine-based, you are prompted to select which Microengine register to watch.
Note: The Workbench now supports setting data watches on the PCI CSRs, but only in hardware
debugging mode.
The CSR categories are:
•
CAP
•
Microengine
•
Memory
•
MSF
•
PCI (only in hardware debugging mode)
•
Intel XScale
•
Microengine Memory
•
MSF Buffers
The Workbench also collects history for:
•
Local Memory
•
CAM
•
Microengine CSRs
— T_INDEX
— NN_PUT
— NN_GET
— ACTIVE_LM_ADDR_0_BYTE_INDEX
— ACTIVE_LM_ADDR_1_BYTE_INDEX
— CTX_ENABLES
Named Elements:
To add a data watch by selecting a named element from a list:
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