Format Of A Page Table Entry - Intel i86W Manual

PRESENT
WRITABLE
USER
WRITE-THROUGH
ADDRESSING
CACHE DISABLE - - - - - - - - - - - - - - - - . . ,
ACCESSED - - - - - - - - - - - - - - - - - - ,
DIRTY - - - - - - - - - - - - - - - - - - ,
(RESERVED)
AVAILABLE FOR SYSTEMS PROGRAMMER USE
1
PAGE FRAME ADDRESS 31 •• 12
NOTE: X INDICATES INTEL RESERVED. DO NOT USE.
Figure 4-5. Format of a Page Table Entry
4.2.4.2 PRESENT BIT
, r
1
5 3
o
240329i
The P (present) bit indicates whether a page table entry can be used in address transla-
tion. P
=
1 indicates that the entry can be used.
When P
=
0 in either level of page tables, the entry is not valid for address translation,
and the rest of the entry is available for software use; none of the other bits in the entry
is tested by the hardware. Figure 4-6 illustrates the format of a page-table entry when
p=o.
If P
=
0 in either level of page tables when an attempt is made to use a page-table entry
for address translation, the processor signals either a data-access fault or an instruction-
access fault. In software systems that support paged virtual memory, the trap handler
can bring the required page into physical memory. Refer to Chapter 7 for more infor-
mation on trap handlers.
AVAILABLE
240329i
Figure 4·6. Invalid Page Table Entry
4-5