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Intel 80960HA Datasheet

32-bit high-performance superscalar processor
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80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor

Product Features

32-Bit Parallel Architecture
— Load/Store Architecture
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— 1.28 Gbyte Internal Bandwidth
(80 MHz)
— On-Chip Register Cache
Processor Core Clock
— 80960HA is 1x Bus Clock
— 80960HD is 2x Bus Clock
— 80960HT is 3x Bus Clock
Binary Compatible with Other 80960
Processors
Issue Up To 150 Million Instructions per
Second
High-Performance On-Chip Storage
— 16 Kbyte Four-Way Set-Associative
Instruction Cache
— 8 Kbyte Four-Way Set-Associative Data
Cache
— 2 Kbyte General Purpose RAM
Separate 128-Bit Internal Paths For
Instructions/Data
3.3 V Supply Voltage
— 5 V Tolerant Inputs
— TTL Compatible Outputs
Guarded Memory Unit
— Provides Memory Protection
— User/Supervisor Read/Write/Execute
32-Bit Demultiplexed Burst Bus
— Per-Byte Parity Generation/Checking
— Address Pipelining Option
— Fully Programmable Wait State Generator
— Supports 8-, 16- or 32-Bit Bus Widths
— 160 Mbyte/s External Bandwidth
(40 MHz)
High-Speed Interrupt Controller
— Up to 240 External Interrupts
— 31 Fully Programmable Priorities
— Separate, Non-maskable Interrupt Pin
Dual On-Chip 32-Bit Timers
— Auto Reload Capability and One-Shot
— CLKIN Prescaling, divided by 1, 2, 4 or 8
— JTAG Support - IEEE 1149.1 Compliant
Order Number: 272495-008
Datasheet
September 2002

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  Summary of Contents for Intel 80960HA

  • Page 1: Product Features

    — Sixteen 32-Bit Local Registers — 1.28 Gbyte Internal Bandwidth (80 MHz) — On-Chip Register Cache Processor Core Clock — 80960HA is 1x Bus Clock — 80960HD is 2x Bus Clock — 80960HT is 3x Bus Clock Binary Compatible with Other 80960 Processors...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
  • Page 3: Table Of Contents

    Contents About This Document ... 9 Intel 80960Hx Processor ... 9 ® The i960 Processor Family ...10 Key 80960Hx Features ...10 2.2.1 Execution Architecture ...10 2.2.2 Pipelined, Burst Bus ...10 2.2.3 On-Chip Caches and Data RAM...11 2.2.4 Priority Interrupt Controller...11 2.2.5...
  • Page 4 Contents VCC5 Current-Limiting Resistor ... 38 AC Test Load... 45 CLKIN Waveform... 46 10 Output Delay Waveform ... 46 11 Output Delay Waveform ... 46 12 Output Float Waveform ... 47 13 Input Setup and Hold Waveform ... 47 14 NMI, XINT7:0 Input Setup and Hold Waveform... 47 15 Hold Acknowledge Timings ...
  • Page 5 Fail Codes For BIST (bit 7 = 1) ...12 Remaining Fail Codes (bit 7 = 0) ...12 80960Hx Instruction Set ...13 80960HA/HD/HT Package Types and Speeds...14 Pin Description Nomenclature ...15 80960Hx Processor Family Pin Descriptions...16 80960Hx 168-Pin PGA Pinout—Signal Name Order...22 80960Hx 168-Pin PGA Pinout—Pin Number Order ...24...
  • Page 6: Removed Operating Frequency Of 16/32 (Bus/Core) From 80960Hd

    • Removed operating frequency of 16/32 (bus/core) from 80960HD. • Removed operating frequency of 20/60 (bus/core) from 80960HT. Table 5 “80960HA/HD/HT Package Types and Speeds” on page • Removed core speed of 32 MHz and bus speed of 16 MHz, and order number A80960HD32-S-L2GG from the 168L PGA package, 80960HD device.
  • Page 7: July 1998

    • Changed ‘5’ to ‘0’ on the CLKIN Frequency axis. Figure 49 “BREQ and BSTALL Operation” on page • Added figure and following text. Fixed several font and format issues. History and T to reflect specific 80960HA, 80960HD TVEL Contents...
  • Page 8 Contents This page intentionally left blank. Datasheet...
  • Page 9: About This Document

    32-bit, RISC-style, embedded processors allows customers to create scalable designs that meet multiple price and performance points. This is accomplished by providing processors that may run at the bus speed or faster using Intel’s clock multiplying technology (see Table 1).
  • Page 10: The I960 ® Processor Family

    Processor Family ® The i960 processor family is a 32-bit RISC architecture created by Intel to serve the needs of embedded applications. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and communications. Because all members of the i960 processor family share a common core architecture, i960 applications are code-compatible.
  • Page 11: On-Chip Caches And Data Ram

    Both signal a fault to the processor. The programmable protection modes are: user read, write or execute; and supervisor read, write or execute. Datasheet 1, the 80960Hx provides generous on-chip cache and storage features to 80960HA/HD/HT...
  • Page 12: Dual Programmable Timers

    80960HA/HD/HT 2.2.6 Dual Programmable Timers The processor provides two independent 32-bit timers, with four programmable clock rates. The user configures the timers through the Timer Unit registers. These registers are memory-mapped within the 80960Hx, addressable on 32-bit boundaries. The timers have a single-shot mode and auto-reload capabilities for continuous operation.
  • Page 13: Instruction Set Summary

    Processor Mgmt Flush Local Registers Modify Arithmetic Controls Atomic Add Modify Process Controls Atomic Modify Interrupt Enable/ Disable System Control 80960HA/HD/HT Logical Bit / Bit Field / Byte Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit...
  • Page 14: Package Information

    Pin Grid Array (PGA) package, 208-pin PowerQuad2* (PQ4). For complete package specifications and information, see the Intel Packaging Handbook (Order# 240800). The 80960HA/HD/HT is offered with eight speeds and two package types 168-pin ceramic Pin Grid Array (PGA) and the 208-pin PowerQuad2* (PQ4) devices are specified for operation at V Table 5.
  • Page 15: Pin Descriptions

    H(Q) continues to be a valid output B(1) is driven to V B(0) is driven to V B(Z) floats B(Q) continues to be a valid output R(1) is driven to V R(0) is driven to V R(Z) floats R(Q) continues to be a valid output 80960HA/HD/HT...
  • Page 16: 80960Hx Processor Family Pin Descriptions

    80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4) Name Type H(Z) A31:2 B(Z) R(Z) S(L) D31:0 H(Z) B(Z) R(Z) S(L) DP3:0 H(Z) B(Z) R(Z) H(Q) PCHK B(Q) R(1) H(Z) BE3:0 B(Z) R(1) H(Z) B(Z) R(0) H(Z)
  • Page 17 (e.g., a semaphore). LOCK is asserted in the first clock of an atomic operation and de- asserted when BLAST is deasserted in the last bus cycle. 80960HA/HD/HT Description and N...
  • Page 18 80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4) Name Type HOLD S(L) H(1) HOLDA B(0) R(Q) BOFF S(L) H(Q) BREQ B(Q) R(0) H(Q) BSTALL B(Q) R(0) H(Z) CT3:0 B(Z) R(Z) XINT7:0 A(E) A(L) A(E) HOLD REQUEST signals that an external agent requests access to the processor’s address, data, and control buses.
  • Page 19: 80960Hx Dc Characteristics

    3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is available only on the PGA version. 0 = 80960Hx 1 = 80960Cx 80960HA/HD/HT Description definition in Table 22, 40. Pull this pin high when not in use.
  • Page 20: 80960Hx Mechanical Data

    80960HA/HD/HT 80960Hx Mechanical Data 3.2.1 80960Hx PGA Pinout Figure 2 depicts the complete 80960Hx PGA pinout as viewed from the top side of the component (i.e., pins facing down). pin-side of the package (i.e., pins facing up). location. See Section 4.3, “Recommended Connections” on page 38 recommended connections.
  • Page 21: 80960Hx 168-Pin Pga Pinout-View From Bottom (Pins Facing Up)

    Figure 3. 80960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up) BOFF FAIL STEST VOLDET TRST PCHK VCCPLL XINT1 XINT0 RESET XINT3 XINT2 XINT5 Datasheet ONCE VCC5 Package Lid CLKIN XINT4 XINT6 XINT7 80960HA/HD/HT READY D28 BTERM HOLDA HOLD BLAST DT/R BSTALL WAIT BREQ LOCK...
  • Page 22 80960HA/HD/HT Table 8. 80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet 1 of 2) Signal Name Signal Name Signal Name BLAST BOFF BREQ BSTALL BTERM CLKIN Signal Name LOCK ONCE PCHK READY RESET STEST TRST DT/R FAIL — — — —...
  • Page 23: 80960Hx 168-Pin Pga Pinout-Signal Name Order

    Table 8. 80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet 2 of 2) Signal Name VCC5 Datasheet Signal Name Signal Name VCCPLL VOLDET 80960HA/HD/HT Signal Name WAIT XINT0 XINT1 XINT2 XINT3 XINT4 XINT5 XINT6 XINT7 — —...
  • Page 24 80960HA/HD/HT Table 9. 80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet 1 of 2) Signal Name FAIL VOLDET TRST XINT1 RESET XINT2 BOFF STEST PCHK VCCPLL Signal Name Signal Name XINT0 XINT3 XINT5 ONCE VCC5 CLKIN XINT4 XINT6 XINT7 Signal Name...
  • Page 25: 80960Hx 168-Pin Pga Pinout-Pin Number Order

    Table 9. 80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet 2 of 2) Signal Name Datasheet Signal Name Signal Name BTERM HOLD 80960HA/HD/HT Signal Name BSTALL BREQ BLAST DT/R WAIT LOCK READY HOLDA...
  • Page 26: 80960Hx Pq4 Pinout

    80960HA/HD/HT 3.2.2 80960Hx PQ4 Pinout Figure 4. 80960Hx 208-Pin PQ4 Pinout PIN 156 PIN 157 XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 RESET CLKIN VCCPLL PCHK TRST VCC5 STEST PIN 208 PIN 1 i960 ® FC80960Hx XXXXXXXX SS © 19xx...
  • Page 27: 80960Hx Pq4 Pinout-Signal Name Order

    Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet 1 of 2) Signal Name Datasheet Signal Name Signal Name BLAST BOFF BREQ BSTALL BTERM CLKIN 80960HA/HD/HT Signal Name PCHK READY RESET STEST TRST DT/R FAIL — — — — — —...
  • Page 28 80960HA/HD/HT Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet 2 of 2) Signal Name Signal Name Signal Name VCC5 VCCPLL Signal Name WAIT XINT0 XINT1 XINT2 XINT3 XINT4 XINT5 XINT6 XINT7 — Datasheet —...
  • Page 29: 80960Hx Pq4 Pinout-Pin Number Order

    Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet 1 of 2) Signal Name FAIL ONCE BOFF Datasheet Signal Name Signal Name 80960HA/HD/HT Signal Name BSTALL BTERM READY HOLD LOCK BREQ HOLDA BLAST DT/R WAIT...
  • Page 30 80960HA/HD/HT Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet 2 of 2) Signal Name Signal Name Signal Name XINT7 XINT6 XINT5 XINT4 Signal Name XINT3 XINT2 PCHK XINT1 XINT0 TRST RESET CLKIN VCC5 VCCPLL STEST Datasheet...
  • Page 31: Package Thermal Specifications

    80960Hx is Figure (thermal resistance from case to ambient) using – allowable (without exceeding T CLKIN as tabulated in and V of 3.3 V. 80960HA/HD/HT ) at various airflows and Section 4.6, “DC...
  • Page 32: 80960Hx 168-Pin Pga Package Thermal Characteristics

    80960HA/HD/HT Table 12. Maximum T at Various Airflows in °C (PGA Package Only) with Heatsink Core 1X Bus Clock without Heatsink with Heatsink Core 2X Bus Clock without Heatsink with Heatsink Core 3X Bus Clock without Heatsink † *0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
  • Page 33: 80960Hx 208-Pin Pq4 Package Thermal Characteristics

    3. 0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Datasheet CLKIN (MHz) (1.01) † † † Thermal Resistance — °C/Watt Airflow — ft./min (m/sec) (1.01) (2.03) (3.07) 80960HA/HD/HT Airflow-ft/min (m/sec) (2.03) (3.04) (4.06) 1000 (4.06) (5.07) 1000 (5.07)
  • Page 34: Heat Sink Adhesives

    80960HA/HD/HT Heat Sink Adhesives Intel recommends silicone-based adhesives to attach heat sinks to the PGA package. There is no particular recommendation concerning the PQ4 package. PowerQuad4 Plastic Package The 80960Hx family is available in an improved version of the common 208-lead SQFP plastic package called the PowerQuad4* (PQ4).
  • Page 35: 80960Hx Device Id Model Types

    Version Product Type Generation Type Model Manufacturer ID Table 17. 80960Hx Device ID Model Types Device 80960HA 80960HD 80960HT Table 18. Device ID Version Numbers for Different Steppings Stepping B0, B2 NOTE: This data sheet applies to the B2 stepping.
  • Page 36: Sources For Accessories

    80960HA/HD/HT Sources for Accessories The following is a list of suggested sources for 80960Hx accessories. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. Sockets • 3M Textool Test and Interconnection Products 6801 River Place Blvd.
  • Page 37: Electrical Specifications

    –0.5 V to VCC5 + 0.5 V Parameter Supply Voltage Input Protection Bias Input Clock Frequency - 1x Core (80960HA) Input Clock Frequency - 2x Core (80960HD) Input Clock Frequency - 3x Core (80960HT) Case Temp Under Bias (PGA and PQ4 Packages)
  • Page 38: Recommended Connections

    80960HA/HD/HT Recommended Connections Power and ground connections must be made to multiple V 80960Hx-based circuit board should include power (V distribution. Every V connected to the ground plane. Pins identified as “NC” —no connect pins—must not be connected in the system.
  • Page 39: Vccpll Pin Requirements

    The VCCPL low-pass filter recommended in the Developer’s Manual does not promote this problem. Datasheet Units VCC5 input should not exceed V 2.25 power-up and power-down, or during steady-state operation. 80960HA/HD/HT Notes by more than 2.25 V during pin voltage by 0.5 V at any pins are driven by separate...
  • Page 40: Dc Specifications

    Test (ONCE mode) Section 4.3, “Recommended Connections” on page Parameter – 0.3 – 0.2 Non-Test Inputs Non-Test Outputs TDO pin 80960HA 25 80960HD 32 80960HT 60 80960HA 25 80960HD 32 1034 80960HT 60 80960HA 25 80960HD 32 80960HT 60 Units Notes +0.8...
  • Page 41 Section 4.7.1, “AC Test Conditions” on page and fall to V = 3.45 V. This parameter is characterized but not tested. values that are tested when the 80960HA/HD/HT is in Reset mode = 3.45 V. = 3.45 V, 0 °C.
  • Page 42: Ac Specifications

    80960HA/HD/HT A.C. Specifications Table 23. 80960Hx A.C. Characteristics (Sheet 1 of 2) Per conditions in Section 4.2, “Operating Conditions” on page 37 Symbol CLKIN Frequency 80960HD CLKIN Period 80960HA 80960HD CLKIN Period Stability CLKIN High Time CLKIN Low Time 80960HD...
  • Page 43 Section 4.7.1, “AC Test Conditions” on page Parameter READY, BTERM, HOLD, and READY, BTERM, HOLD, and 1, 2, 3, 6, 10 Relative Output Timings 80960HA 80960HD 80960HT 1, 7, 10 Relative Input Timings for all notes related to AC specifications.
  • Page 44: 80960Hx Boundary Scan Test Signal Timings

    80960HA/HD/HT Table 24. A.C. Characteristics Notes NOTES: 1. See Section 4.8, “AC Timing Waveforms” on page 46 2. See Figure 25, “Output Delay or Hold vs. Load Capacitance” on page 52 for output delays and hold times. 3. See Figure 22, “Rise and Fall Time Derating at 85 °C and Minimum VCC” on page 51 derating information for rise and fall times.
  • Page 45: Ac Test Conditions

    80960HA/HD/HT 4.7.1 A.C. Test Conditions A.C. values are derived using the 50 pF load shown in Figure Figure 25, “Output Delay or Hold vs. Load Capacitance” on page 52, shows how timings vary with load capacitance. Input waveforms (except for CLKIN) are assumed to have a rise and fall time of 2 ns from 0.8 V to 2.0 V.
  • Page 46: Ac Timing Waveforms

    80960HA/HD/HT A.C. Timing Waveforms Figure 9. CLKIN Waveform Figure 10. Output Delay Waveform A31:2, D31:0 write only, DP3:0 write only PCHK, BE3:0, W/R, D/C, SUP, ADS, DEN, LOCK, HOLDA, BREQ, BSTALL, CT3:0, FAIL, WAIT, BLAST Figure 11. Output Delay Waveform 1.5 V...
  • Page 47: Output Float Waveform

    A and B edges are established by de-assertion of RESET. See Datasheet 1.5 V CLKIN Outputs: LOCK, HOLDA, CLKIN 1.5 V Inputs: CLKIN 1.5 V 1.5 V 80960HA/HD/HT 1.5 V 1.5 V 1.5 V Valid 1.5 V 1.5 V 1.5 V Valid Figure 29, “Cold Reset Waveform” on page...
  • Page 48: Hold Acknowledge Timings

    80960HA/HD/HT Figure 15. Hold Acknowledge Timings — OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay (T The minimum output delay is referred to as the Output Hold (T — INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation.
  • Page 49: Tck Waveform

    Figure 18. Input Setup and Hold Waveforms for T TCLK Inputs: Datasheet BSCR BSCF BSCH and T BSIS1 1.5 V 1.5 V BSIH1 BSIS1 Valid 1.5 V 80960HA/HD/HT 2.0 V 1.5 V 0.8 V BSCL BSIH1 1.5 V 1.5 V...
  • Page 50 80960HA/HD/HT Figure 19. Output Delay and Output Float for T Figure 20. Output Delay and Output Float Waveform for T Non-Test Outputs Figure 21. Input Setup and Hold Waveform for T Non-Test Inputs and T BSOV1 BSOF1 1.5 V 1.5 V...
  • Page 51 Figure 22. Rise and Fall Time Derating at 85 °C and Minimum V 50pF Figure 23. I Active (Power Supply) vs. Frequency 1800 1600 1400 1200 1000 Datasheet 100pF (pF) CLKIN Frequency (MHz) 80960HA/HD/HT 2.0 to 0.8 V 0.8 to 2.0 V 150pF...
  • Page 52: Output Delay Or Hold Vs. Load Capacitance

    80960HA/HD/HT Figure 24. I Active (Thermal) vs. Frequency 1400 1200 1000 Figure 25. Output Delay or Hold vs. Load Capacitance CLKIN Frequency (MHz) nom + 10 5.5 V Input Signals nom + 5 3.3 V Input Signals (pF) Datasheet...
  • Page 53: Output Delay Vs. Temperature

    + 0.5 nom + 0.4 nom + 0.3 nom + 0.2 nom + 0.1 nom + 0 nom + 0.5 nom + 0.3 nom + 0.1 -nom + 0.1 -nom + 0.3 -nom + 0.5 3.15 (volts) 80960HA/HD/HT 85°C 85°C 3.45...
  • Page 54: Bus Waveforms

    CLKIN VCC5, ONCE CT3:0, ADS, LOCK, WAIT, DEN, BLAST W/R, DT/R, BREQ, FAIL, BSTALL A31:2, SUP D/C, BE3:0 D31:0, Inputs DP3:0 STEST RESET CLKIN and V minimum 10,000 CLKIN periods for PLL stabilization. NOTE: stable: As specified in Table 21, “VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)” on page 39 Invalid Valid Thold...
  • Page 55 CLKIN ADS, LOCK, WAIT, DEN, BLAST, W/R, BREQ, FAIL, BSTALL DT/R SUP, A31:2, D/C, BE3:0 D31:0, DP3:0 STEST Maximum Low to RESET 16 CLKIN Periods RESET Valid State RESET Tsetup Thold 1 CLKIN 1 CLKIN RESET High to First Bus Activity, HA=67, HD=34, HT=23 CLKIN Periods Minimum RESET Low Time...
  • Page 56 CLKIN VCC5 ADS, BE3:0, A31:2, D31:0, LOCK, WAIT, BLAST,W/R, D/C, DEN, DT/R, HOLDA, BLAST, FAIL, SUP,BREQ, CT3:0, BSTALL, DP3:0, PCHK ONCE mode is entered within 1 CLKIN period after ONCE becomes low while RESET is low. RESET ONCE CLKIN and V RESET high, minimum 10,000 CLKIN Periods.
  • Page 57: Non-Burst, Non-Pipelined Requests Without Wait States

    D/C, BE3:0, LOCK, CT3:0 BLAST DT/R D31:0, DP3:0 PCHK Datasheet Pipe- Parity Ready Burst Lining Parity Enable Width 23-22 Disabled Enabled Bits 31-30, 27-25, 13, and 5 are reserved. Valid WAIT 80960HA/HD/HT 19-16 15-14 12-8 00000 0000 00000 Valid Valid...
  • Page 58: Non-Burst, Non-Pipelined Read Request With Wait States

    80960HA/HD/HT Figure 33. Non-Burst, Non-Pipelined Read Request with Wait States PMCON Function Value NOTE: CLKIN A31:2, BE3:0 BLAST DT/R D/C, SUP, LOCK, CT3:0 WAIT D31:0, DP3:0 PCHK External Pipe- Parity Ready Burst Lining Parity Enable Width Control 23-22 Disabled Disabled Enabled Bits 31-30, 27-25, 13, and 5 are reserved.
  • Page 59: Non-Burst, Non-Pipelined Write Request With Wait States

    LOCK, CT3:0 WAIT D31:0, DP3:0 PCHK Datasheet External Pipe- Ready Burst Lining Parity Enable Width Control 23-22 Disabled Enabled Disabled NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. Valid Valid 80960HA/HD/HT Parity 19-16 15-14 12-8 xxxxx 00011 0001 xxxxx...
  • Page 60: Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus

    80960HA/HD/HT Figure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus PMCON Function Value CLKIN A31:4, SUP, CT3:0,D/C, BE3:0, LOCK BLAST DT/R A3:2 WAIT D31:0, DP3:0 PCHK External Pipe- Ready Burst Lining Parity Width Control 23-22 Disabled Enabled 32-Bit NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
  • Page 61: Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus

    CT3:0, D/C, BE3:0, LOCK BLAST DT/R A3:2 WAIT D31:0, DP3:0 PCHK Datasheet Pipe- Parity Ready Burst Lining Parity Enable Width Control 23-22 Enabled Enabled 32-Bit Bits 31-30, 27-25, 13, and 5 are reserved. 80960HA/HD/HT 19-16 15-14 12-8 xxxxx 0001 00010 Valid...
  • Page 62: Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus

    80960HA/HD/HT Figure 37. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus PMCON External Function Ready Control Disabled Value NOTE: CLKIN A31:4, SUP, CT3:0, D/C, BE3:0, LOCK BLAST DT/R A3:2 WAIT D31:0, DP3:0 PCHK Pipe- Parity Burst Lining Parity Enable...
  • Page 63: Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus

    BE3:0, LOCK BLAST DT/R A3:2 WAIT D31:0, DP3:0 PCHK Datasheet Pipe- Parity Burst Lining Parity Enable Width 23-22 32-bit Enabled Enabled Bits 31-30, 27-25, 13, and 5 are reserved. Valid Out0 Out1 80960HA/HD/HT 19-16 15-14 12-8 00010 0001 xxxxx Out3 Out2...
  • Page 64: Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus

    80960HA/HD/HT Figure 39. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus PMCON External Function Ready Control Disabled Value NOTE: CLKIN SUP, CT3:0, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE BLAST DT/R A3:2 BE1/A1 WAIT D31:0, DP3:0 PCHK Pipe- Parity Burst Lining...
  • Page 65: Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus

    Disabled Enabled Enabled NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A3:2 = 00, 01, 10 or 11 A1:0 = 00 A1:0 = 01 D7:0 Byte 0 80960HA/HD/HT Parity 19-16 15-14 12-8 xxxxx 0001 00010 Valid A1:0 = 10...
  • Page 66: Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus

    80960HA/HD/HT Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Function Ready Control Value NOTE: CLKIN A31:4, SUP, CT3:0, D/C, LOCK A3:2 BE3:0 D31:0, DP3:0 WAIT BLAST DT/R PCHK 1. Non-pipelined request concludes, pipelined reads begin.
  • Page 67: Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus

    1. Non-pipelined request concludes, pipelined reads begin 2. Pipelined reads conclude, non-pipelined requests begin Datasheet Pipe- Parity Burst Lining Parity Enable Width 23-22 19-16 32-Bit Disabled Enabled A’ Valid Valid Valid Valid 80960HA/HD/HT 15-14 12-8 xxxx xxxxx 00001 D ’ Invalid Invalid Invalid D’...
  • Page 68: Burst, Pipelined Read Request Without Wait States, 32-Bit Bus

    80960HA/HD/HT Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Function Ready Control Value NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A31:4, SUP, CT3:0, D/C, BE3:0, LOCK Pipe- Parity Burst Lining Width Parity Enable...
  • Page 69: Burst, Pipelined Read Request With Wait States, 32-Bit Bus

    1. Non-pipelined request concludes, pipelined reads begin. 2. Pipelined reads conclude, non-pipelined requests begin. Datasheet Pipe- Parity Burst Lining Parity Enable Width 23-22 32-Bit Enabled Enabled Valid 80960HA/HD/HT 19-16 15-14 12-8 xxxx xxxxx A’ D’ Valid valid valid Valid valid 00010 D’...
  • Page 70: Burst, Pipelined Read Request With Wait States, 8-Bit Bus

    80960HA/HD/HT Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus PMCON External Function Ready Control Value NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. CLKIN A31:4, SUP, CT3:0, D/C, LOCK A3:2 BE1/A1, BE0/A0 D31:0, DP3:0 WAIT BLAST...
  • Page 71: Burst, Pipelined Read Request With Wait States, 16-Bit Bus

    Burst Lining Parity Enable Width 23-22 16-Bit Enabled Enabled Valid A3:2 = 00 or 10 A3:2 = 01 or 11 D15:0 D15:0 A1=0 A1=1 80960HA/HD/HT 19-16 15-14 12-8 xxxx xxxxx 00010 A’ D’ Valid valid valid Valid valid Valid valid...
  • Page 72: Using External Ready

    80960HA/HD/HT Figure 47. Using External READY CLKIN A31:4, SUP, CT3:0, D/C, BE3:0, LOCK BLAST DT/R READY BTERM A3:2 WAIT D31:0, DP3:0 PCHK NOTE: Pipelining must be disabled to use READY. Quad-Word Read Request = 0, N = 0, N Ready Enabled...
  • Page 73: Terminating A Burst With Bterm

    BTERM interrupts a bus access, whether or not the bus access has more data transfers pending. Either the READY signal or the BTERM signal terminates a bus access when the signal is asserted during the last (or only) data transfer of the bus access. 80960HA/HD/HT...
  • Page 74: Breq And Bstall Operation

    80960HA/HD/HT Figure 49. BREQ and BSTALL Operation CLKIN BLAST BREQ BSTALL The processor may stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted). Depending on the instruction stream and memory wait states, the two signals may be separated by several CLKIN cycles.
  • Page 75: Boff Functional Timing. Boff Occurs During A Burst Or Non-Burst Data Cycle

    Note: READY/BTERM must be enabled; N Datasheet BOFF Mode Non-Burst May Change Suspend Request Valid Begin Request BOFF may be asserted to suspend request BOFF may not be asserted 80960HA/HD/HT Regenerate ADS Burst Resume Request Valid End Request BOFF may not be asserted...
  • Page 76: Hold Functional Timing

    80960HA/HD/HT Figure 51. HOLD Functional Timing Word Read Request Word Read Request Hold State Hold State CLKIN A31:2, SUP, CT3:0, D/C, Valid Valid BE3:0, WAIT, DEN, DT/R BLAST LOCK HOLD HOLDA Datasheet...
  • Page 77: Lock Delays Holda Timing

    Figure 52. LOCK Delays HOLDA Timing CLKIN BLAST LOCK HOLD HOLDA Figure 53. FAIL Functional Timing RESET FAIL 80960HA: 80960HD: 80960HT: Datasheet (Internal Self-Test) Pass Fail 113 Cycles 257,517 Cycles 30 Cycles 15 Cycles 94 Cycles 128,761 Cycles 85,840 Cycles...
  • Page 78: A Summary Of Aligned And Unaligned Transfers For 32-Bit Regions

    80960HA/HD/HT Figure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions Byte Offset Word Offset Short-Word Load/Store Word Load/Store Double-Word Load/Store NOTES: 1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes adjacent requests to occur for full words to the same address.
  • Page 79: A Summary Of Aligned And Unaligned Transfers For 32-Bit Regions (Continued)

    Datasheet One Three-Word Request (Aligned) Trey, Byte, Trey, Byte, Trey, Byte Requests Short, Short, Short, Short Short, Short, Short Requests Byte, Trey, Byte, Trey, Byte, Trey Requests 80960HA/HD/HT Word, Word, Word Requests Word, Word, Word Requests Word, Word, Word Requests...
  • Page 80: A Summary Of Aligned And Unaligned Transfers For 16-Bit Bus

    80960HA/HD/HT Figure 56. A Summary of Aligned and Unaligned Transfers for 16-Bit Bus Byte Offset Word Offset Short 16-Bit Bus Word 16-Bit Bus Double Word 16-Bit Bus Triple Word 16-Bit Bus Quad Word 16-Bit Bus Short Byte, Byte Short Byte, Byte...
  • Page 81: A Summary Of Aligned And Unaligned Transfers For 8-Bit Bus

    (Two Byte Burst) *4 (Byte, Three Byte Burst) *2 (Four Byte Burst) *2 (Four Byte Burst)*3 (Three Byte Burst, Byte)*3 (Two Byte Burst) *6 80960HA/HD/HT (Four Byte Burst) *2 (Byte, Three Byte Burst) *3 (Four Byte Burst)*3 (Four Byte Burst)*3 (Four Byte Burst)*4...
  • Page 82: Idle Bus Operation

    80960HA/HD/HT Figure 58. Idle Bus Operation CLKIN A31:4, SUP, D/C, BE3:0, CT3:0 LOCK BLAST DT/R A3:2 WAIT D31:0 READY, BTERM PCHK Write Request Idle Bus =2, N (not in Hold Acknowledge state) Ready Disabled Valid Valid Valid Valid Read Request...
  • Page 83: Bus States

    CNT=1 and HOLD !HOLD and W CNT=1 and !REQUEST HOLD HOLD !HOLD 80960HA/HD/HT CNT = 1 READ and N > 0 or WRITE and N > 0 !BOFF and READ and N and !BLAST or !BOFF and WRITE and N...
  • Page 84: 80960Hx Boundary Scan Chain

    80960HA/HD/HT 80960Hx Boundary Scan Chain Table 26. 80960Hx Boundary Scan Chain (Sheet 1 of 4) STEST FAILBAR Enable for FAILBAR, BSTALL and BREQ ONCEBAR BOFFBAR Enable for DP(3:0) and D(31:0) NOTES: 1. Cell#1 connects to TDO and cell #112 connects to TDI.
  • Page 85 Output Output Control Output Output Output Output Control 80960HA/HD/HT Comment Appears as READYBAR in BSDL file. Appears as BEBAR(3:0) in BSDL file. Appears as WRBAR in BSDL file. Appears as DCBAR in BSDL file. Appears as SUPBAR in BSDL file.
  • Page 86 80960HA/HD/HT Table 26. 80960Hx Boundary Scan Chain (Sheet 3 of 4) LOCKBAR BREQ Enable for A(31:0) and CT(3:0) NMIBAR NOTES: 1. Cell#1 connects to TDO and cell #112 connects to TDI. 2. All outputs are tri-state. 3. In output and bidirectional signals, a logical 1 on the enable signal enables the output. A logical 0 tri-states the output.
  • Page 87 Boundary Scan Cell Cell Type Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Control 80960HA/HD/HT Comment Appears as XINTBAR(7:0) in BSDL file. Appears as CT(3:0) in BSDL file. Appears as PCHKBAR in BSDL file.
  • Page 88: Boundary Scan Description Language Example

    -- Copyright Intel Corp. 1995 - - *************************************************************************** - - Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
  • Page 89 3); : out bit; : out bit; : out bit; : in bit; : out bit; : out bit; : in bit; : in bit; : out bit; : in bit; : in bit; : in bit; 80960HA/HD/HT...
  • Page 90 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 3 of 8) SUPBAR TRST WAITBAR WRBAR XINTBAR FIVEVREF VCCPLL VOLTDET VCC1 VCC2 VSS1 VSS2 use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP; constant PGA:PIN_MAP_STRING := “A...
  • Page 91 B12, C14, E15, F16, H16, J16, K16, M16, N15, Q06,”& R07, R08, R10, R11),”& : (G03, H03, J03, K03, L03, M03, C07, C08, C09, C10,”& C11, C12, Q07, Q08, Q09, Q10, Q11, F15, G15, H15,”& J15, K15, L15, M15, A01, C04),”& : (A09, A10, B13, B14, D03)”; 80960HA/HD/HT...
  • Page 92 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 5 of 8) attribute Tap_Scan_In attribute Tap_Scan_Mode attribute Tap_Scan_Out attribute Tap_Scan_Reset of attribute Tap_Scan_Clock of attribute Instruction_Length of Ha_Processor: entity is 4; attribute Instruction_Opcode of Ha_Processor: entity is “BYPASS...
  • Page 93 D(16), bidir, D(17), bidir, D(18), bidir, D(19), bidir, D(20), bidir, D(21), bidir, D(22), bidir, D(23), bidir, D(24), bidir, 17, 1, 80960HA/HD/HT Z),” & Z),” & Z),” & Z),” & & Z),” & & & & Z),” & Z),” & Z),”...
  • Page 94 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 7 of 8) “35 (CBSC_1, “36 (CBSC_1, “37 (CBSC_1, “38 (CBSC_1, “39 (CBSC_1, “40 (CBSC_1, “41 (CBSC_1, “42 (BC_4, “43 (BC_4, “44 (BC_4, “45 (BC_1, “46 (BC_1, “47 (BC_1, “48 (BC_1,...
  • Page 95 80, 1, CT(2), output3, 80, 1, Z),” CT(1), output3, 80, 1, Z),” CT(0), output3, 80, 1, Z),” PCHKBAR, output3, 111, 1, Z),” control, 1)”; 80960HA/HD/HT Z),” & Z),” & Z),” & Z),” & Z),” & Z),” & & Z),” &...
  • Page 96 -- Copyright Intel Corporation 1995, 1996 -- ***************************************************************************** -- Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
  • Page 97 : in bit; : out bit; : in bit; : in bit; : out bit; : in bit; : in bit; : out bit; : out bit; : in bit_vector(0 to 7); : linkage bit; : linkage bit; 80960HA/HD/HT...
  • Page 98 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 3 of 8) VCC1 VCC2 VSS1 VSS2 use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP; constant PQ2:PIN_MAP_STRING := “A “ “ “ADSBAR “BEBAR “BLASTBAR “BOFFBAR...
  • Page 99 : (108, 114, 116, 122, 129, 130, 136, 142, 148, 152,”& 155, 156, 157, 164, 170, 172, 178, 184, 186, 190,”& 195, 198, 200, 205)”; : signal is true; : signal is true; : signal is true; TRST : signal is true; : signal is (66.0e6, BOTH); 80960HA/HD/HT...
  • Page 100 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 5 of 8) “BYPASS “EXTEST “SAMPLE “IDCODE “RUBIST “CLAMP “HIGHZ “Reserved attribute Instruction_Capture of Ha_Processor: entity is “0001”; attribute Instruction_Private of Ha_Processor: entity is “Reserved” ; attribute Idcode_Register of Ha_Processor: entity is “0001”...
  • Page 101 D(21), bidir, D(22), bidir, D(23), bidir, D(24), bidir, D(25), bidir, D(26), bidir, D(27), bidir, D(28), bidir, D(29), bidir, D(30), bidir, 80960HA/HD/HT & & & Z),” & Z),” & Z),” & Z),” & Z),” & Z),” & Z),” & Z),” &...
  • Page 102 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 7 of 8) “41 (CBSC_1, “42 (BC_4, “43 (BC_4, “44 (BC_4, “45 (BC_1, “46 (BC_1, “47 (BC_1, “48 (BC_1, “49 (BC_1, “50 (BC_1, “51 (BC_1, “52 (BC_1, “53 (BC_1, “54 (BC_1,...
  • Page 103 X),” CT(3), output3, 80, 1, CT(2), output3, 80, 1, CT(1), output3, 80, 1, CT(0), output3, 80, 1, PCHKBAR, output3, 111,1, control, 1)”; 80960HA/HD/HT Z),” & Z),” & Z),” & Z),” & & Z),” & Z),” & Z),” & Z),” &...
  • Page 104 80960HA/HD/HT This page intentionally left blank. Datasheet...

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