Cpu Data Bus Transfer Control; Memory Bus Mode Selection - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
SRAM to read data for a line fill even before the cycle has been guaranteed to complete on the
memory bus via BGT#.
The Address bus runs at the same clock frequency as the CPU bus (CLK). The memory data
bus runs at a speed equal to or less than CLK (MCLK).
Data transfer ... o and out of the 82491 Cache SRAMs take place in clocked mode or in
strobed mode. The data transfer mode may be selected independently of the snoop mode.
5.1.4.1. CPU DATA BUS TRANSFER CONTROL
The Pentium processor latches or drives data upon active sampling of the BRDY# input from
the MBC or the BRDYC# input from the 82496 Cache Controller. It is very important to data
transfer timings that all of the processor chip set components receive equivalent data control
signals. Therefore, it is a requirement that the MBC provide the Pentium processor, 82496
Cache Controller cache controller, and all 82491 Cache SRAMs with the same BRDY# input.
The 82496 Cache Controller also provides the Pentium processor and 82491 Cache SRAM
functionally equivalent BRDYC# signals. See Figure 5-19 for clarification on BRDY# /
BRDYC# / BRDYC1# / BRDYC2# interconnection between the processor chip set
components.
5.1.5.
PENTIUM ™ PROCESSOR
~
BROY#
BROYC#
'I'
MBC
BROYC1#
BROY#
"-
BROY# BROYC2#
,
82496
82491
~
BROYC#
BROY#
_t
• •
•
CDB52
Figure 5-19. BRDY# / BRDYC#
I
BRDYC1# / BRDYC2# Interconnection
Memory Bus Mode Selection
Clocked memory bus mode and Strobed memory bus mode determine how the MBC transfers
data into and out of the 82491 Cache SRAM.
In clocked mode, data is driven with reference to the Memory Clock (MCLK) input. MCLK is
supplied by the MBC and can be of any frequency (within specs). To avoid the need for
synchronization, MCLK may be such that the CPU clock frequency is a multiple of MCLK
5-24
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