Memory Data Routing Example; Control Signals - Scke[3:0], Scs#[3:0]; Figure 39. Data Signals Group Routing Example - Intel 855GM Design Manual

R
6.3.4.6.

Memory Data Routing Example

Figure 39 is an example of a board routing for the Data signal group. The majority of the Data signal
route is on an internal layer, both external layers can be used for parallel termination R-pack placement.

Figure 39. Data Signals Group Routing Example

6.3.5. Control Signals – SCKE[3:0], SCS#[3:0]
The GMCH control signals, SCKE[3:0] and SCS#[3:0], are clocked into the DDR SDRAM devices
using clock signals SCK/SCK#[5:0]. The GMCH drives the control and clock signals together, with the
clocks crossing in the valid control window. The GMCH provides one chip select (CS) and one clock
enable (CKE) signal per SO-DIMM physical device row. Two chip select and two clock enable signals
will be routed to each SO-DIMM. Refer to Table 29 for the CKE and CS# signal to SO-DIMM
mapping.
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Intel 855GM/855GME Chipset Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration
From GMCH
Data Signals
91