Table 76. Stm32Wl5X Peripherals Interconnect Matrix - ST STM32WL55JC Reference Manual

RM0453
12.3.2 From timer (LPTIM1/LPTIM2) to timer (LPTIM3)
Purpose
Some timers are linked together internally for synchronization or chaining.
When one timer is configured in Master mode, it can reset, start, stop or clock the counter of
another timer configured in Slave mode. A description of the feature is provided in
Section 25.3.26: Timer
Triggering signals
The output is on signals LPTIMx_OUT following a configurable timer event. The input (to
slave) is on signals LPTIM3_ETR.
The input and output signals for LPTIM are shown in
diagram.
The possible connections are given
Active power modes
Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1
12.3.3 From timer (TIM1/TIM2) and GPIO pin EXTI to ADC/DAC
Purpose
Advanced-control timer TIM1, general-purpose timer TIM2 and GPIO pin EXTI can be used
to generate an ADC/DAC trigger event.
TIMx synchronization is described in
GPIO pin EXTI mux is described in
ADC synchronization is described in
trigger polarity (EXTSEL,
DAC synchronization is described in
Triggering signals
The output from timer is on signals TIMx_TRGO, TIMx_TRGO2, TIMx_CCx, TIMx_CHn
event. The output from GPIO pin is on EXTI mux signal from SYSCFG.
The input to ADC is on signals TRG[7:0].
The connection between timers, GPIO pin EXTI mux and ADC, is provided
External
The input to DAC is on signals dac_ch1_trg[15:0].
The connection between timers, GPIO pin EXTI mux and DAC, is provided
DAC interconnection.
Active power modes
Run, Sleep, LPRun, LPSleep
synchronization.
EXTEN).
triggers.
Figure 261: Low-power timer block
inTable 194: LPTIM3 external trigger
Section 25.3.27: ADC
Section 11: System configuration controller
Section 18.4: Conversion on external trigger and
Section 19.4.7: DAC trigger
RM0453 Rev 2
Peripherals interconnect matrix
connection.
synchronization.
selection.
inTable 102:
inTable 114:
(SYSCFG).
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