Low Frequency Trigger Mode; Data Management; Data Register And Data Alignment (Adc_Dr, Align); Adc Overrun (Ovr, Ovrmod) - ST STM32WL5 Series Reference Manual

Analog-to-digital converter (ADC)
18.4.6

Low frequency trigger mode

Once the ADC is enabled or the last ADC conversion is complete, the ADC is ready to start
a new conversion. The ADC needs to be started at a predefined time (t
converted data might be corrupted due to the transistor leakage (refer to the device
datasheet for the maximum value of t
If the application has to support a time longer than the maximum t
trigger to another for single conversion mode or between the ADC enable and the first ADC
conversion), then the ADC internal state needs to be rearmed. This mechanism can be
enabled by setting LFTRIG bit to 1 in ADC_CFGR2 register. By setting this bit, any trigger
(software or hardware) sends a rearm command to ADC. The conversion is started after a
two ADC clock cycle delay compared to LFTRIG set to 0.
It is not necessary to use this mode when AUTOFF bit is set to 1. For Wait mode, only the
first trigger generates an internal rearm command.
18.5

Data management

18.5.1

Data register and data alignment (ADC_DR, ALIGN)

At the end of each conversion (when an EOC event occurs), the result of the converted data
is stored in the ADC_DR data register which is 16-bit wide.
The format of the ADC_DR depends on the configured data alignment and resolution.
The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after
conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in
Figure 71.

Figure 71. Data alignment and resolution (oversampling disabled: OVSE = 0)

15
ALIGN RES
0
0x0
0x1
0x2
0x3
1
0x0
0x1
0x2
0x3
18.5.2

ADC overrun (OVR, OVRMOD)

The overrun flag (OVR) indicates a data overrun event, when the converted data was not
read in time by the CPU or the DMA, before the data from a new conversion is available.
The OVR flag is set in the ADC_ISR register if the EOC flag is still at '1' at the time when a
new conversion completes. An interrupt can be generated if the OVRIE bit is set in the
ADC_IER register.
552/1461
14 13 12 11 10
0x0
0x00
0x00
0x00
DR[9:0]
DR[7:0]
0x00
RM0453 Rev 1
).
idle
9 8 7 6
DR[11:0]
DR[11:0]
DR[5:0]
) otherwise ADC
idle
value (between one
idle
5 4 3 2 1
DR[9:0]
DR[7:0]
DR[5:0]
0x0
0x00
0x00
0x0
RM0453
0
MS30342V1