Software Interrupt Event Register (Exti_Swier); Pending Register (Exti_Pr) - ST STM32F100 Series Reference Manual

Interrupts and events
8.3.5

Software interrupt event register (EXTI_SWIER)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
15 14 13
SWIER SWIER SWIER SWIER
15 14 13
rw rw rw
Bits 31:18 Reserved, must be kept at reset value (0).
Bits 17:0 SWIERx: Software interrupt on line x
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0'
sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit)
8.3.6

Pending register (EXTI_PR)

Address offset: 0x14
Reset value: undefined
31 30 29
15 14 13
PR15 PR14 PR13 PR12
rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:18 Reserved, must be kept at reset value (0).
Bits 17:0 PRx: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is
cleared by writing a '1' into the bit.
142/709
28 27 26 25
Reserved
12 11 10 9
SWIER SWIER SWIER
12 11 10 9
rw rw rw rw
28 27 26 25
Reserved
12 11 10 9
PR11 PR10 PR9
rc_w1 rc_w1 rc_w1
24 23 22
8 7 6
SWIER SWIER SWIER SWIER
8 7 6
rw rw rw
24 23 22
8 7 6
PR8 PR7 PR6 PR5
rc_w1 rc_w1 rc_w1 rc_w1
RM0041 Rev 6
21 20 19 18
5 4 3 2
SWIER SWIER SWIER
5 4 3 2
rw rw rw rw
21 20 19 18
5 4 3 2
PR4 PR3 PR2
rc_w1 rc_w1 rc_w1
RM0041
17 16
SWIER SWIER
17 16
rw rw
1 0
SWIER SWIER
1 0
rw rw
17 16
PR17 PR16
rc_w1 rc_w1
1 0
PR1 PR0
rc_w1 rc_w1