Pending Register (Exti_Pr) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

Interrupts and events

Pending register (EXTI_PR)

Address offset: 0x14

Reset value: undefined

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 PR[22:21]: Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by programming it to '1'.

Bits 20:19 Reserved, must be kept at reset value.

Bits 18:0 PR[18:0]: Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by programming it to '1'.

RM0402 Rev 6

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