Renesas H8S Series Hardware Manual page 313

Bit Bit Name Initial Value
7 POE3M1 0
6 POE3M0 0
5 POE2M1 0
4 POE2M0 0
3 POE1M1 0
2 POE1M0 0
Section 11 Motor Management Timer (MMT)
R/W Description
R/W POE3 Modes 1 and 0
These bits select the input mode of the POE3 pin.
R/W
00: Request accepted at falling edge of POE3 input
01: POE3 input is sampled for low level 16 times
every φ/8 clock, and request is accepted when
all samples are low level
10: POE3 input is sampled for low level 16 times
every φ/16 clock, and request is accepted when
all samples are low level
11: POE3 input is sampled for low level 16 times
every φ/128 clock, and request is accepted
when all samples are low level
R/W POE2 Modes 1 and 0
These bits select the input mode of the POE2 pin.
R/W
00: Request accepted at falling edge of POE2 input
01: POE2 input is sampled for low level 16 times
every φ/8 clock, and request is accepted when
all samples are low level
10: POE2 input is sampled for low level 16 times
every φ/16 clock, and request is accepted when
all samples are low level
11: POE2 input is sampled for low level 16 times
every φ/128 clock, and request is accepted
when all samples are low level
R/W POE1 Modes 1 and 0
These bits select the input mode of the POE1 pin.
R/W
00: Request accepted at falling edge of POE1 input
01: POE1 input is sampled for low level 16 times
every φ/8 clock, and request is accepted when
all samples are low level
10: POE1 input is sampled for low level 16 times
every φ/16 clock, and request is accepted when
all samples are low level
11: POE1 input is sampled for low level 16 times
every φ/128 clock, and request is accepted
when all samples are low level
Rev. 6.00 Mar 15, 2006 page 277 of 570
REJ09B0211-0600