Timer Mode Register (Tmdr) - Renesas H8S Series Hardware Manual

Section 11 Motor Management Timer (MMT)
• Timer general register VD (TGRVD)
• Timer general register WD (TGRWD)
• Timer dead time counter 0 (TDCNT0)
• Timer dead time counter 1 (TDCNT1)
• Timer dead time counter 2 (TDCNT2)
• Timer dead time counter 3 (TDCNT3)
• Timer dead time counter 4 (TDCNT4)
• Timer dead time counter 5 (TDCNT5)
• Timer dead time data register (TDDR)
• Timer period buffer register (TPBR)
• Timer period data register (TPDR)
• MMT pin control register (MMTPC)
11.3.1

Timer Mode Register (TMDR)

The timer mode register (TMDR) sets the operating mode and selects the PWM output level.
Bit Bit Name
7 to 4 —
3 OLSN
2 OLSP
1 MD1
0 MD0
Rev. 6.00 Mar 15, 2006 page 248 of 570
REJ09B0211-0600
Initial Value R/W
All 0 —
0 R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
These bits are always read as 0 and should only be
written with 0.
Output Level Select N
Selects the negative phase output level in the
operating modes.
0: Active level is low
1: Active level is high
Output Level Select P
Selects the positive phase output level in the
operating modes.
0: Active level is low
1: Active level is high
Modes 0 to 3
These bits set the timer operating mode.
00: Operation halted
01: Operating mode 1 (transfer at crest)
10: Operating mode 2 (transfer at trough)
11: Operating mode 3 (transfer at crest and trough)