Renesas H8S Series Hardware Manual page 27

Section 11 Motor Management Timer (MMT)
Figure 11.1 Block Diagram of MMT ....................................................................................... 246
Figure 11.2 Sample Operating Mode Setting Procedure .......................................................... 254
Figure 11.3 MMT Canceling Procedure................................................................................... 255
Figure 11.4 Example of TCNT Count Operation ..................................................................... 256
Figure 11.5 Examples of Counter and Register Operations...................................................... 257
Figure 11.6 Example of PWM Waveform Generation ............................................................. 260
Figure 11.7 Example of TCNT Counter Clearing .................................................................... 261
Figure 11.8 Example of Toggle Output Waveform Synchronized with PWM Period ............. 262
Figure 11.9 Count Timing ........................................................................................................ 264
Figure 11.10 TCNT Counter Clearing Timing ........................................................................... 264
Figure 11.11 TDCNT Operation Timing.................................................................................... 265
Figure 11.12 Dead Time Generation Timing.............................................................................. 266
Figure 11.13 Buffer Operation Timing....................................................................................... 267
Figure 11.14 TGI Interrupt Timing ............................................................................................ 268
Figure 11.15 Timing of Status Flag Clearing by CPU................................................................ 269
Figure 11.16 Timing of Status Flag Clearing by DTC Controller .............................................. 269
Figure 11.17 Contention between Buffer Register Write and Compare Match.......................... 270
Figure 11.18 Contention between Compare Register Write and Compare Match...................... 271
Figure 11.19 Error Case in Writing Operation ........................................................................... 272
Figure 11.20 Output Waveform Caused by Dead Time Limitation ........................................... 273
Figure 11.21 Block Diagram of POE ......................................................................................... 274
Figure 11.22 Low Level Detection Operation ............................................................................ 279
Section 12 Programmable Pulse Generator (PPG)
Figure 12.1 Block Diagram of PPG.......................................................................................... 282
Figure 12.2 PPG Output Operation .......................................................................................... 291
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) ............................... 292
Figure 12.4 Setup Procedure for Normal Pulse Output (Example) .......................................... 293
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output)................................... 294
Figure 12.6 Non-Overlapping Pulse Output ............................................................................. 295
Figure 12.7 Non-Overlapping Operation and NDR Write Timing ........................................... 296
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example) .......................... 297
Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary).............. 298
Figure 12.10 Inverted Pulse Output (Example) .......................................................................... 300
Figure 12.11 Pulse Output Triggered by Input Capture (Example)............................................ 301
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of WDT........................................................................................ 304
Figure 13.2 Writing to TCNT, TCSR, and RSTCSR (Example for WDT0) ............................ 310
Figure 13.3 Contention between TCNT Write and Increment.................................................. 311
Rev. 6.00 Mar 15, 2006 page xxvii of xxxvi