Renesas H8S Series Hardware Manual page 323

Bit Bit Name
7 to —
4
3 NDR11
2 NDR10
1 NDR9
0 NDR8
NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit Bit Name
7 NDR7
6 NDR6
5 NDR5
4 NDR4
3 NDR3
2 NDR2
1 NDR1
0 NDR0
Initial Value R/W
All 1 —
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Section 12 Programmable Pulse Generator (PPG)
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Next Data Register 8 to11
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
Description
Next Data Register 0 to 7
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Rev. 6.00 Mar 15, 2006 page 287 of 570
REJ09B0211-0600