Renesas H8S Series Hardware Manual page 16

10.2 Input/Output Pins .............................................................................................................. 163
10.3 Register Descriptions ........................................................................................................ 164
10.3.1 Timer Control Register (TCR) ............................................................................. 166
10.3.2 Timer Mode Register (TMDR) ............................................................................ 171
10.3.3 Timer I/O Control Register (TIOR) ..................................................................... 173
10.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 190
10.3.5 Timer Status Register (TSR)................................................................................ 192
10.3.6 Timer Counter (TCNT)........................................................................................ 195
10.3.7 Timer General Register (TGR) ............................................................................ 195
10.3.8 Timer Start Register (TSTR)................................................................................ 195
10.3.9 Timer Synchro Register (TSYR) ......................................................................... 196
10.4 Operation .......................................................................................................................... 197
10.4.1 Basic Functions.................................................................................................... 197
10.4.2 Synchronous Operation........................................................................................ 203
10.4.3 Buffer Operation .................................................................................................. 205
10.4.4 Cascaded Operation ............................................................................................. 209
10.4.5 PWM Modes ........................................................................................................ 211
10.4.6 Phase Counting Mode .......................................................................................... 216
10.5 Interrupts ........................................................................................................................... 223
10.6 DTC Activation................................................................................................................. 225
10.7 A/D Converter Activation ................................................................................................. 225
10.8 Operation Timing.............................................................................................................. 226
10.8.1 Input/Output Timing ............................................................................................ 226
10.8.2 Interrupt Signal Timing........................................................................................ 230
10.9 Usage Notes ...................................................................................................................... 234
10.9.1 Module Stop Mode Setting .................................................................................. 234
10.9.2 Input Clock Restrictions ...................................................................................... 234
10.9.3 Caution on Period Setting .................................................................................... 234
10.9.4 Contention between TCNT Write and Clear Operations..................................... 235
10.9.5 Contention between TCNT Write and Increment Operations.............................. 236
10.9.6 Contention between TGR Write and Compare Match ......................................... 237
10.9.7 Contention between Buffer Register Write and Compare Match ........................ 238
10.9.8 Contention between TGR Read and Input Capture.............................................. 239
10.9.9 Contention between TGR Write and Input Capture............................................. 240
10.9.10 Contention between Buffer Register Write and Input Capture ............................ 241
10.9.11 Contention between Overflow/Underflow and Counter Clearing........................ 242
10.9.12 Contention between TCNT Write and Overflow/Underflow............................... 243
10.9.13 Multiplexing of I/O Pins ...................................................................................... 243
10.9.14 Interrupts in Module Stop Mode.......................................................................... 243
Rev. 6.00 Mar 15, 2006 page xvi of xxxvi