Pc Break Set For Instruction Fetch At Address Following Bcc Instruction; Pc Break Set For Instruction Fetch At Branch Destination Address Of Bcc Instruction - Renesas H8S Series Hardware Manual

Section 6 PC Break Controller (PBC)
disabled for a 3-state period in the case of LDC, ANDC, ORC, and XOR, the next instruction is
always executed. For details, see section 5, Interrupt Controller.
6.4.7

PC Break Set for Instruction Fetch at Address Following Bcc Instruction

When a PC break is set for an instruction fetch at an address following a Bcc instruction:
A PC break interrupt is generated if the instruction at the next address is executed in accordance
with the branch condition, and is not generated if the instruction at the next address is not
executed.
6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc
Instruction
When a PC break is set for an instruction fetch at the branch destination address of a Bcc
instruction:
A PC break interrupt is generated if the instruction at the branch destination is executed in
accordance with the branch condition, and is not generated if the instruction at the branch
destination is not executed.
Rev. 6.00 Mar 15, 2006 page 96 of 570
REJ09B0211-0600