Table 8.5 Dtc Execution Status; Table 8.6 Number Of States Required For Each Execution Status - Renesas H8S Series Hardware Manual

Section 8 Data Transfer Controller (DTC)
Table 8.5 DTC Execution Status
Vector Read
Mode I
Normal 1
Repeat 1
Block transfer 1
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 8.6 Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
Execution Vector read
status
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation
Note: * Cannot be used in this LSI.
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · (1 + S
For example, when the DTC vector address table is located in the on-chip ROM, normal mode is
set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for
the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev. 6.00 Mar 15, 2006 page 122 of 570
REJ09B0211-0600
Register Information
Read/Write
J
6
6
6
On- On-
Chip Chip
RAM ROM
32 16
1 1
S — 1
I
1 —
S
J
S 1 1
K
S 1 1
K
S 1 1
L
S 1 1
L
S
M
) + Σ (J · S
I
Data Read Data Write
K L
1 1
1 1
N N
On-Chip I/O
External Devices *
Registers
8 16 8
2 2 2
— — 4
— — —
2 2 2
4 2 4
2 2 2
4 2 4
1
+ K · S + L · S
J K L
Internal
Operations
M
3
3
3
16
3 2 3
6 + 2m 2 3 + m
— — —
3 + m 2 3 + m
6 + 2m 2 3 + m
3 + m 2 3 + m
6 + 2m 2 3 + m
) + M · S
M