Section 1 Overview
MD2
MD1
MD0
EXTAL
XTAL
PLLVCL
PLLCAP
PLLVSS
STBY
RES
NC
NMI
PF7/φ
PF6
PF5
PF4
PF3/ADTRG/IRQ3
PF2
PF1
PF0/IRQ2
Figure 1.2 Internal Block Diagram (HD6432616 and HD6432614)
Rev. 6.00 Mar 15, 2006 page 4 of 570
REJ09B0211-0600
H8S/2600 CPU
Interrupt controller
ROM
(mask ROM)
RAM
TPU × 6 channels
Port 1
Port D
WDT × 1 channel
SCI × 3 channels
HCAN × 1 channel
A/D converter
Port 4
PA3/SCK2
PA2/RxD2
PA1/TxD2
PA0
PB7/TIOCB5
PB6/TIOCA5
PB5/TIOCB4
PB4/TIOCA4
PB3/TIOCD3
PB2/TIOCC3
PB1/TIOCB3
PB0/TIOCA3
PC7
PC6
PC5/SCK1/IRQ5
PC4/RxD1
PC3/TxD1
PC2/SCK0/IRQ4
PC1/RxD0
PC0/TxD0
P93/AN11
P92/AN10
P91/AN9
P90/AN8