Renesas H8S Series Hardware Manual page 21

15.8.3 HCAN Sleep Mode .............................................................................................. 434
15.8.4 Interrupts.............................................................................................................. 434
15.8.5 Error Counters...................................................................................................... 434
15.8.6 Register Access.................................................................................................... 434
15.8.7 HCAN Medium-Speed Mode .............................................................................. 434
15.8.8 Register Hold in Standby Modes ......................................................................... 434
15.8.9 Usage of Bit Manipulation Instructions ............................................................... 434
15.8.10 HCAN TXCR Operation...................................................................................... 435
Section 16 A/D Converter
16.1 Features ............................................................................................................................. 437
16.2 Input/Output Pins .............................................................................................................. 439
16.3 Register Description.......................................................................................................... 440
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 440
16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 441
16.3.3 A/D Control Register (ADCR) ............................................................................ 443
16.4 Operation .......................................................................................................................... 444
16.4.1 Single Mode......................................................................................................... 444
16.4.2 Scan Mode ........................................................................................................... 444
16.4.3 Input Sampling and A/D Conversion Time ......................................................... 445
16.4.4 External Trigger Input Timing............................................................................. 447
16.5 Interrupts ........................................................................................................................... 447
16.6 A/D Conversion Precision Definitions.............................................................................. 448
16.7 Usage Notes ...................................................................................................................... 450
16.7.1 Module Stop Mode Setting .................................................................................. 450
16.7.2 Permissible Signal Source Impedance ................................................................. 450
16.7.3 Influences on Absolute Precision......................................................................... 450
16.7.4 Range of Analog Power Supply and Other Pin Settings ...................................... 451
16.7.5 Notes on Board Design ........................................................................................ 451
16.7.6 Notes on Noise Countermeasures ........................................................................ 451
Section 17 RAM
Section 18 ROM
18.1 Features ............................................................................................................................. 455
18.2 Mode Transitions .............................................................................................................. 456
18.3 Block Configuration.......................................................................................................... 460
18.4 Input/Output Pins .............................................................................................................. 461
18.5 Register Descriptions ........................................................................................................ 462
18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 462
18.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 464
................................................................................................. 437
.................................................................................................................. 453
.................................................................................................................. 455
Rev. 6.00 Mar 15, 2006 page xxi of xxxvi