Renesas H8S Series Hardware Manual page 362

Section 14 Serial Communication Interface (SCI)
Bit Bit Name Initial Value
2 TEND 1
1 MPB 0
0 MPBT 0
Rev. 6.00 Mar 15, 2006 page 326 of 570
REJ09B0211-0600
R/W Description
R Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DTC is activated by a TXI interrupt and
writes data to TDR
R Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous
state is retained.
R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit data.