Table 10.21 Tiorl_0 (Channel 0) - Renesas H8S Series Hardware Manual

Table 10.21 TIORL_0 (channel 0)

Bit 3 Bit 2 Bit 1
IOC3 IOC2 IOC1
0 0 0
1
1 0
1
1 0 0
1
1 X
Legend:
X: Don't care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Bit 0 TGRC_0
IOC0 Function
0 Output
compare
1
register *
0
1
0
1
0
1
0 Input
capture
1
register *
X
X
Section 10 16-Bit Timer Pulse Unit (TPU)
Description
TIOCC_0 Pin Function
Output disabled
Initial output is 0
0 output at compare match
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Rev. 6.00 Mar 15, 2006 page 183 of 570
REJ09B0211-0600