Renesas H8S Series Hardware Manual page 227

Bit Bit Name Initial value
2 TGIEC 0
1 TGIEB 0
0 TGIEA 0
Section 10 16-Bit Timer Pulse Unit (TPU)
R/W Description
R/W TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
R/W TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
R/W TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Rev. 6.00 Mar 15, 2006 page 191 of 570
REJ09B0211-0600