Section 8 Data Transfer Controller (DTC)
Interrupt controller
Interrupt
request
CPU interrupt
request
Legend:
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERG:
DTVECR:
Rev. 6.00 Mar 15, 2006 page 104 of 570
REJ09B0211-0600
DTC
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to G
DTC vector register
Figure 8.1 Block Diagram of DTC
Internal address bus
Internal data bus
On-chip
RAM