Renesas H8S Series Hardware Manual page 13

5.6.1 Interrupt Control Mode 0 ..................................................................................... 79
5.6.2 Interrupt Control Mode 2 ..................................................................................... 81
5.6.3 Interrupt Exception Handling Sequence .............................................................. 83
5.6.4 Interrupt Response Times .................................................................................... 85
5.6.5 DTC Activation by Interrupt................................................................................ 86
5.7 Usage Notes ...................................................................................................................... 86
5.7.1 Contention between Interrupt Generation and Disabling..................................... 86
5.7.2 Instructions that Disable Interrupts ...................................................................... 87
5.7.3 When Interrupts are Disabled .............................................................................. 87
5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 88
Section 6 PC Break Controller (PBC)
6.1 Features ............................................................................................................................. 89
6.2 Register Descriptions ........................................................................................................ 90
6.2.1 Break Address Register A (BARA) ..................................................................... 90
6.2.2 Break Address Register B (BARB)...................................................................... 91
6.2.3 Break Control Register A (BCRA) ...................................................................... 91
6.2.4 Break Control Register B (BCRB)....................................................................... 92
6.3 Operation .......................................................................................................................... 92
6.3.1 PC Break Interrupt Due to Instruction Fetch ....................................................... 92
6.3.2 PC Break Interrupt Due to Data Access............................................................... 92
6.3.3 Notes on PC Break Interrupt Handling ................................................................ 93
6.3.4 Operation in Transitions to Power-Down Modes ................................................ 93
6.3.5 When Instruction Execution is Delayed by One State ......................................... 94
6.4 Usage Notes ...................................................................................................................... 95
6.4.1 Module Stop Mode Setting .................................................................................. 95
6.4.2 PC Break Interrupts.............................................................................................. 95
6.4.3 CMFA and CMFB ............................................................................................... 95
6.4.4 PC Break Interrupt when DTC is Bus Master...................................................... 95
6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP,
TRAPA, RTE, or RTS Instruction ....................................................................... 95
6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction ....................................... 95
6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction.......... 96
6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc
Instruction ............................................................................................................ 96
Section 7 Bus Controller
7.1 Basic Timing ..................................................................................................................... 97
7.1.1 On-Chip Memory Access Timing (ROM, RAM) ................................................ 97
7.1.2 On-Chip Support Module Access Timing............................................................ 98
7.1.3 On-Chip HCAN Module Access Timing ............................................................. 99
........................................................................... 89
................................................................................................... 97
Rev. 6.00 Mar 15, 2006 page xiii of xxxvi