Usage Notes; Module Stop Mode Setting; Notes For Mmt Operation; Figure 11.17 Contention Between Buffer Register Write And Compare Match - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer
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Section 11 Motor Management Timer (MMT)
11.7

Usage Notes

11.7.1

Module Stop Mode Setting

MMT operation can be disabled or enabled using the module stop control register. The initial
setting is for MMT operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 20, Power-Down Modes.
11.7.2

Notes for MMT Operation

Note that the kinds of operation and contention described below occur during MMT operation.
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T
state of a buffer register (TBRU to TBRW, or TPBR) write cycle, data is transferred from
2
the buffer register to the compare register (TGR or TPDR) by a buffer operation. The data
transferred is the buffer register write data.
Figure 11.17 shows the timing in this case.
φ
Address
Write signal
Compare match
signal
TGI interrupt
Buffer register
Compare register

Figure 11.17 Contention between Buffer Register Write and Compare Match

Rev. 6.00 Mar 15, 2006 page 270 of 570
REJ09B0211-0600
Buffer register
write cycle
T
T
T
1
2
3
Buffer register address
Buffer register write data
N
M
M

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