Appendix; On-Chip I/O Register; Register Addresses - Renesas H8S Series Hardware Manual

Note: MMT, DTC, PBC, and PPG functions are not implemented in the H8S/2614 and
H8S/2616.
A.

On-Chip I/O Register

A.1

Register Addresses

Register Name
Master control register
General status register
Bit configuration register
Mailbox configuration register
Transmit wait register
Transmit wait cancel register
Transmit acknowledge register
Abort acknowledge register
Receive complete register
Remote request register
Interrupt register
Mailbox interrupt mask register
Interrupt mask register
Receive error counter
Transmit error counter
Unread message status register
Local acceptance filter mask L
Local acceptance filter mask H
Message control 0[1]
Message control 0[2]
Message control 0[3]
Message control 0[4]
Message control 0[5]

Appendix

Abbrevia-
Bit No. Address * Module
tion
MCR 8
GSR 8
BCR 16
MBCR 16
TXPR 16
TXCR 16
TXACK 16
ABACK 16
RXPR 16
RFPR 16
IRR 16
MBIMR 16
IMR 16
REC 8
TEC 8
UMSR 16
LAFML 16
LAFMH 16
MC0[1] 8
MC0[2] 8
MC0[3] 8
MC0[4] 8
MC0[5] 8
Rev. 6.00 Mar 15, 2006 page 523 of 570
H'F800 HCAN
H'F801 HCAN
H'F802 HCAN
H'F804 HCAN
H'F806 HCAN
H'F808 HCAN
H'F80A HCAN
H'F80C HCAN
H'F80E HCAN
H'F810 HCAN
H'F812 HCAN
H'F814 HCAN
H'F816 HCAN
H'F818 HCAN
H'F819 HCAN
H'F81A HCAN
H'F81C HCAN
H'F81E HCAN
H'F820 HCAN
H'F821 HCAN
H'F822 HCAN
H'F823 HCAN
H'F824 HCAN
Appendix
Data Access
Width State
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
16 4
REJ09B0211-0600